JPS577927A - Manufacture of semiconductor - Google Patents

Manufacture of semiconductor

Info

Publication number
JPS577927A
JPS577927A JP8264680A JP8264680A JPS577927A JP S577927 A JPS577927 A JP S577927A JP 8264680 A JP8264680 A JP 8264680A JP 8264680 A JP8264680 A JP 8264680A JP S577927 A JPS577927 A JP S577927A
Authority
JP
Japan
Prior art keywords
diffused
minute
impurities
region
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8264680A
Other languages
Japanese (ja)
Inventor
Takashi Sugino
Kunio Ito
Masaru Wada
Yuichi Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP8264680A priority Critical patent/JPS577927A/en
Publication of JPS577927A publication Critical patent/JPS577927A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
    • H10P32/141—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer comprising oxides only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material

Landscapes

  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To enable to introduce impurities in a minute region by introducing the impurities into a semiconductor substrate through a layer having the different thicknesses at the different parts. CONSTITUTION:On the semiconductor substrate 5, is provided an impurity introduction controlling layer 6 having the different thicknesses at the different parts thereof. A diffusion preventing film 7 is provided at the thin part, and the impurities are diffused to form impurity diffused regions 8 and 9. Then the impurity introduction controlling layer 6 is removed so that the minute diffused region 9 is remained. In this method, expansion in the lateral direction is suppressed, and the minute diffused region having good reproducibility can be formed.
JP8264680A 1980-06-17 1980-06-17 Manufacture of semiconductor Pending JPS577927A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8264680A JPS577927A (en) 1980-06-17 1980-06-17 Manufacture of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8264680A JPS577927A (en) 1980-06-17 1980-06-17 Manufacture of semiconductor

Publications (1)

Publication Number Publication Date
JPS577927A true JPS577927A (en) 1982-01-16

Family

ID=13780186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8264680A Pending JPS577927A (en) 1980-06-17 1980-06-17 Manufacture of semiconductor

Country Status (1)

Country Link
JP (1) JPS577927A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5211776A (en) * 1975-07-17 1977-01-28 Toshiba Corp Method of manufacturing semiconductor device
JPS5219984A (en) * 1975-08-07 1977-02-15 Nippon Telegr & Teleph Corp <Ntt> Manufacture process for a isolation layer used to make a semiconductor element

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5211776A (en) * 1975-07-17 1977-01-28 Toshiba Corp Method of manufacturing semiconductor device
JPS5219984A (en) * 1975-08-07 1977-02-15 Nippon Telegr & Teleph Corp <Ntt> Manufacture process for a isolation layer used to make a semiconductor element

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