JPS5779633A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5779633A
JPS5779633A JP55154577A JP15457780A JPS5779633A JP S5779633 A JPS5779633 A JP S5779633A JP 55154577 A JP55154577 A JP 55154577A JP 15457780 A JP15457780 A JP 15457780A JP S5779633 A JPS5779633 A JP S5779633A
Authority
JP
Japan
Prior art keywords
region
substrate
silicon
layer
single crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55154577A
Other languages
Japanese (ja)
Inventor
Masaru Ihara
Yoshihiro Arimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55154577A priority Critical patent/JPS5779633A/en
Publication of JPS5779633A publication Critical patent/JPS5779633A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]

Landscapes

  • Element Separation (AREA)

Abstract

PURPOSE:To enable to integrate a high voltage circuit and a low voltage high speed circuit on the same substrate of a semiconductor device by a method wherein single crystal semiconductor layers being insulated lectrically and having different film thickness are formed on the concave and region of a magnesia spinel layer. CONSTITUTION:After resist masks 4 are formed on the silicon single crystal substrate 3 to cover and protect the upper parts of an element isolation region, the exposed part of the silicon substrate 3 is etched using NaOH, etc., to form a concave region 10. The magnesia spinel layer 2 is formed on the substrate 3, and a silicon epitaxial layer 1 is formed on the upper surface of the layer 2 thereof. A part of the thin film silicon epitaxial layer in the convex regions are oxidized to form silicon dioxide 5, and electric isolation between the adjoining region is attained.
JP55154577A 1980-11-05 1980-11-05 Manufacture of semiconductor device Pending JPS5779633A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55154577A JPS5779633A (en) 1980-11-05 1980-11-05 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55154577A JPS5779633A (en) 1980-11-05 1980-11-05 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5779633A true JPS5779633A (en) 1982-05-18

Family

ID=15587255

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55154577A Pending JPS5779633A (en) 1980-11-05 1980-11-05 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5779633A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61164238A (en) * 1985-01-17 1986-07-24 Toshiba Corp Composite semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61164238A (en) * 1985-01-17 1986-07-24 Toshiba Corp Composite semiconductor device

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