JPS5779749A - Packet transmission system - Google Patents

Packet transmission system

Info

Publication number
JPS5779749A
JPS5779749A JP55155480A JP15548080A JPS5779749A JP S5779749 A JPS5779749 A JP S5779749A JP 55155480 A JP55155480 A JP 55155480A JP 15548080 A JP15548080 A JP 15548080A JP S5779749 A JPS5779749 A JP S5779749A
Authority
JP
Japan
Prior art keywords
frame
register
circuit
reception
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55155480A
Other languages
Japanese (ja)
Inventor
Shufu Kusayanagi
Naruhiro Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55155480A priority Critical patent/JPS5779749A/en
Publication of JPS5779749A publication Critical patent/JPS5779749A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE:To simplify the insertion/removal control of packet frame, by providing a frame buffer for packet insertion period's share to a central control station. CONSTITUTION:The frame information from a loop transmission line is received at a frame reception circuit 20 in a central control station and applied to a frame number interpretation circuit 24 and a storage register 25. The frame number interpreted in this circuit 24 is applied to a register 23 to absorb the transmission/reception clock phase difference, and the reception frame information written in the said register 25 is written in a write-in register 27 with a timing signal from a timing generation circuit 26 and introduced to a frame buffer 29 storing a plurality of frames corresponding to the maximum value of the packet insertion period. The frame information in the buffer 29 is read out at a read-in register 31 under the control of the transmission timing generating circuit 26 and applied to a frame multiplex circuit 35.
JP55155480A 1980-11-05 1980-11-05 Packet transmission system Pending JPS5779749A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55155480A JPS5779749A (en) 1980-11-05 1980-11-05 Packet transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55155480A JPS5779749A (en) 1980-11-05 1980-11-05 Packet transmission system

Publications (1)

Publication Number Publication Date
JPS5779749A true JPS5779749A (en) 1982-05-19

Family

ID=15606961

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55155480A Pending JPS5779749A (en) 1980-11-05 1980-11-05 Packet transmission system

Country Status (1)

Country Link
JP (1) JPS5779749A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS535542A (en) * 1976-07-06 1978-01-19 Toshiba Corp Multiplication circular bus system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS535542A (en) * 1976-07-06 1978-01-19 Toshiba Corp Multiplication circular bus system

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