JPS5784643A - Signal separation circuit - Google Patents

Signal separation circuit

Info

Publication number
JPS5784643A
JPS5784643A JP55161681A JP16168180A JPS5784643A JP S5784643 A JPS5784643 A JP S5784643A JP 55161681 A JP55161681 A JP 55161681A JP 16168180 A JP16168180 A JP 16168180A JP S5784643 A JPS5784643 A JP S5784643A
Authority
JP
Japan
Prior art keywords
output
gate
level
terminal
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55161681A
Other languages
Japanese (ja)
Inventor
Masatoshi Murakawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55161681A priority Critical patent/JPS5784643A/en
Publication of JPS5784643A publication Critical patent/JPS5784643A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Synchronizing For Television (AREA)

Abstract

PURPOSE:To separate and output a plurality of signals from a serial data signal with simple constitution, by combining AND and OR gates. CONSTITUTION:When a pulse of ''1'' lever is supplied to an input terminal B of a signal separation circuit 31, output terminals C and D are at level 0 and 1 at the rise of signal. The output of an OR gate 34 is applied to an AND gate 32, the output of the gate 32 is applied to a gate 34 and the output of the gate 34 is kept at level 1 even if the signal at the terminal B is at level 0. Thus, the output of the terminal D is at level 1. This state is kept until an input terminal A is at level 0, and consequently a signal applied to the terminal A is split to the terminals C,D in the timing of pulse applied to the terminal B.
JP55161681A 1980-11-17 1980-11-17 Signal separation circuit Pending JPS5784643A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55161681A JPS5784643A (en) 1980-11-17 1980-11-17 Signal separation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55161681A JPS5784643A (en) 1980-11-17 1980-11-17 Signal separation circuit

Publications (1)

Publication Number Publication Date
JPS5784643A true JPS5784643A (en) 1982-05-27

Family

ID=15739815

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55161681A Pending JPS5784643A (en) 1980-11-17 1980-11-17 Signal separation circuit

Country Status (1)

Country Link
JP (1) JPS5784643A (en)

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