JPS578912A - Recording and reproducing device for binary data - Google Patents
Recording and reproducing device for binary dataInfo
- Publication number
- JPS578912A JPS578912A JP8349480A JP8349480A JPS578912A JP S578912 A JPS578912 A JP S578912A JP 8349480 A JP8349480 A JP 8349480A JP 8349480 A JP8349480 A JP 8349480A JP S578912 A JPS578912 A JP S578912A
- Authority
- JP
- Japan
- Prior art keywords
- demodulators
- logic
- nrzi
- much
- reducing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
- G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
PURPOSE:To decrease a minimum magnetization inversion interval and the extent of a limit phase shift as much as possible by reducing the number of bits of a logic [0] in succession as much as possible by reducing the number of continuous [0]s in terms of probability. CONSTITUTION:The result of AND between pulses reproduced from an odd-numbered track and an even-numbered track following it is applied to corresponding to NRZI demodulators 31-38. Words having bits inverted in logic by a recording data processor, i.e. the outputs of the NRZI demodulators 32, 34, 36, and 38 among the demodulators 31-38 are supplied to inverters 52, 54, 56, and 58, which restore each bit to its original logic. Thus, each word inputted to a speed converting circuit 7 is rearranged in the word order when an ADC2 is outputted and a decoder circuit 8 checks and corrects an error, so that a DAC9 converts the input into the original audio signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8349480A JPS578912A (en) | 1980-06-18 | 1980-06-18 | Recording and reproducing device for binary data |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8349480A JPS578912A (en) | 1980-06-18 | 1980-06-18 | Recording and reproducing device for binary data |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS578912A true JPS578912A (en) | 1982-01-18 |
Family
ID=13804028
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8349480A Pending JPS578912A (en) | 1980-06-18 | 1980-06-18 | Recording and reproducing device for binary data |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS578912A (en) |
-
1980
- 1980-06-18 JP JP8349480A patent/JPS578912A/en active Pending
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