JPS5793457A - Microprogram controller - Google Patents

Microprogram controller

Info

Publication number
JPS5793457A
JPS5793457A JP55169100A JP16910080A JPS5793457A JP S5793457 A JPS5793457 A JP S5793457A JP 55169100 A JP55169100 A JP 55169100A JP 16910080 A JP16910080 A JP 16910080A JP S5793457 A JPS5793457 A JP S5793457A
Authority
JP
Japan
Prior art keywords
trace
section
instruction
signal
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55169100A
Other languages
Japanese (ja)
Inventor
Keizo Moriya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55169100A priority Critical patent/JPS5793457A/en
Publication of JPS5793457A publication Critical patent/JPS5793457A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To enable tracing of a normal instruction and failure retrieval of a microprogram(MP) controller, by giving a trace function of MP to the MP controller. CONSTITUTION:An MP instruction is read out from an MP storage section 11 to an MP instruction readout section 12 by the instruction of an address register section 13. In a trace instruction section 14, either one of a normal confirming mode bit signal or a failure retrieval mode bit signal is detected according to a trace mode signal (b) and a corresponding trace instruction signal (c) is outputted. A trace address storage control section 16 receiving the signal (c) stores the trace address represented with a trace address signal (d) from the section 13 to a trace address storage section 17. In this case, the trace address corresponding to the mode bit signal indicated with the trace mode signal (b) is stored and transmitted outside the device with a trace content readout section 19.
JP55169100A 1980-12-02 1980-12-02 Microprogram controller Pending JPS5793457A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55169100A JPS5793457A (en) 1980-12-02 1980-12-02 Microprogram controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55169100A JPS5793457A (en) 1980-12-02 1980-12-02 Microprogram controller

Publications (1)

Publication Number Publication Date
JPS5793457A true JPS5793457A (en) 1982-06-10

Family

ID=15880303

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55169100A Pending JPS5793457A (en) 1980-12-02 1980-12-02 Microprogram controller

Country Status (1)

Country Link
JP (1) JPS5793457A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4991153A (en) * 1972-12-29 1974-08-30
JPS5361940A (en) * 1976-11-16 1978-06-02 Nippon Telegr & Teleph Corp <Ntt> Debug system for microprogram

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4991153A (en) * 1972-12-29 1974-08-30
JPS5361940A (en) * 1976-11-16 1978-06-02 Nippon Telegr & Teleph Corp <Ntt> Debug system for microprogram

Similar Documents

Publication Publication Date Title
JPS5345120A (en) Video special effect device
JPS5793457A (en) Microprogram controller
JPS5694596A (en) Memory control system
JPS55163697A (en) Memory device
JPS5736500A (en) Memory check system
JPS57105895A (en) Error detection and correction device
JPS5782298A (en) Diagnostic system for storage device
JPS56162128A (en) Process input/output device
JPS56127257A (en) State history storage device
JPS56105546A (en) Memory mapping circuit
JPS57168355A (en) Operation sequence storing device of microprogram
JPS5781650A (en) Data processor
JPS57183700A (en) Information processor
JPS56117400A (en) Buffer memory control system
JPS57135496A (en) P-rom compensating circuit
JPS56159747A (en) Program testing device
JPS56169295A (en) Error retrieval system of information processor
JPS578999A (en) Memory controller
JPS57197653A (en) Control device of microprogram
JPS57164351A (en) Debugging device
JPS57206988A (en) Data processor
JPS56134398A (en) Check system for error detecting and correcting circuit
JPS54145443A (en) Data memory circuit
JPS56165997A (en) Parity check system for storage device
JPS57107641A (en) Counter read control system