JPS5794861A - Confirming system for running state of program - Google Patents

Confirming system for running state of program

Info

Publication number
JPS5794861A
JPS5794861A JP55170347A JP17034780A JPS5794861A JP S5794861 A JPS5794861 A JP S5794861A JP 55170347 A JP55170347 A JP 55170347A JP 17034780 A JP17034780 A JP 17034780A JP S5794861 A JPS5794861 A JP S5794861A
Authority
JP
Japan
Prior art keywords
instruction
lamp
program
switch
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55170347A
Other languages
Japanese (ja)
Inventor
Hajime Seto
Tetsuo Urushibara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55170347A priority Critical patent/JPS5794861A/en
Publication of JPS5794861A publication Critical patent/JPS5794861A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To confirm the running state of a program, by providing a control means which identifies an instruction to switch on and off a lamp and then switches on and off the lamp and replacing an optional instruction of a route of the program with an instruction to switch on or off the lamp.
CONSTITUTION: A lamp switch-on instruction LON and a lamp switch-off instruction LOF are put into addresses 0100 and 0500 respectively of a program in a memory device MEM. The original instruction is previously saved in a lamp-on register LONR and a lamp-off register LOFR respectively. When a program is started and reaches the address 0100, the instruction LON is supplied to an instruction register IR via a memory buffer register MBR and analyzed by a decoder DEC. This analyzed instruction is supplied to an AND gate and a timing circuit T through a control line 1, and opens the AND gate to go into an FF and to switch on a lamp LAP. The output signal (a) of the circuit T stores the original instruction in an instruction register IR through the LONR to the MBR and executes the instruction. An address 0500 is processed in the same way.
COPYRIGHT: (C)1982,JPO&Japio
JP55170347A 1980-12-03 1980-12-03 Confirming system for running state of program Pending JPS5794861A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55170347A JPS5794861A (en) 1980-12-03 1980-12-03 Confirming system for running state of program

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55170347A JPS5794861A (en) 1980-12-03 1980-12-03 Confirming system for running state of program

Publications (1)

Publication Number Publication Date
JPS5794861A true JPS5794861A (en) 1982-06-12

Family

ID=15903236

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55170347A Pending JPS5794861A (en) 1980-12-03 1980-12-03 Confirming system for running state of program

Country Status (1)

Country Link
JP (1) JPS5794861A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61105649A (en) * 1984-10-29 1986-05-23 Shimadzu Corp Operating status display method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61105649A (en) * 1984-10-29 1986-05-23 Shimadzu Corp Operating status display method

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