JPS5810143U

JPS5810143U - central processing unit

Info

Publication number: JPS5810143U
Application number: JP10047381U
Authority: JP
Inventors: 増本　大和
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 1981-07-06
Filing date: 1981-07-06
Publication date: 1983-01-22
Also published as: JPS6121695Y2

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来の一例を示すブロック図、第２図は本考案
の一実施例を示すブロック図である。１・・・アドレス部、２・・・制御記憶部、３・・・保
持部、４・・・チェック部、５・・・選択部、６・・・
論理部、７・・・クロック部、８・・・アドレス保持回
路、９・・・保持回路、１０・・・チェック回路、１１
・・・アドレス、１２・・・マイクロプログラム語、１
３・・・マ・ｆクロプログラム語、１４・・・マイクロ
プログラム語、１５・・・マイクロプログラム語、１６
・・・アドレス、１０１・・・１ビツト工ラー指示信号
、１０２・・・２ビット以上エラー指示信号、１０３〜
１０５・・・クロック信号、１０６・・・クロック遅延
信号、１０７・・・クロック停止信号、２２・・・マイ
クロプログラム語、１０８・・・エラー信号、１０９・
・・クロック信号、２０１゜２０２・・・アンド回路。FIG. 1 is a block diagram showing a conventional example, and FIG. 2 is a block diagram showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Address part, 2... Control storage part, 3... Holding part, 4... Check part, 5... Selection part, 6...
Logic part, 7... Clock part, 8... Address holding circuit, 9... Holding circuit, 10... Check circuit, 11
...Address, 12...Microprogram word, 1
3... Macro program word, 14... Micro program word, 15... Micro program word, 16
...Address, 101...1 bit error instruction signal, 102...2 or more bit error instruction signal, 103~
105... Clock signal, 106... Clock delay signal, 107... Clock stop signal, 22... Micro program word, 108... Error signal, 109...
...Clock signal, 201°202...AND circuit.

Claims

[Scope of utility model registration request]

a control storage section that stores a microprogram consisting of a microprogram word to which an FCC bit is added; an address section that stores an address for reading out the microtelogram word from the control storage section; and the control storage section. A holding section for holding the microprogram word read out from the holding section, and an FCC check of the microprogram word held in the holding section, and when there is a 1-bit error, the error pit is automatically corrected, and a 1-bit factory instruction signal is also provided. a checking section which outputs a 2-bit or more error indication signal when there is an error of 2 bits or more; a microprogram word outputted from the holding section and a microprogram word after 1-bit error correction outputted from the checking section; a selection section which switches the microprogram according to a 1-bit processor instruction signal; and a selection section which operates according to the microprogram word outputted from the selection section, and which determines the next address of the microprogram and sends the clock to the clock section according to the error signal from the check section. On the other hand, when there is a 1-bit error, a clock delay signal is output that instructs the output timing of the supplied clock signal to be delayed.
a logic section that outputs a clock stop signal instructing to stop the clock in the case of an error of more than one bit; a clock section that supplies a clock signal to the address section, the holding section, and the logic section; and a timing held by the holding section. A holding circuit that holds the microprogram word read out at an earlier timing performs an FCC check on the microprogram word held by the holding circuit, and when the check results in an error, sends an error signal to the logic section. A central processing unit comprising: a check circuit; and an address holding circuit that holds the address when the error signal is supplied.