JPS58105497A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To increase the reliability, by obtaining a binary output without flowing at all times a current to a nonvolatile storage element for a semiconductor integrated circuit having the redundant function and can switch a normal circuit to a spare circuit in case the normal circuit is faulty. CONSTITUTION:For this semiconductor integrated position, a fuse element F made of polysilicon is inserted between the point of application of a power supply VD and an output terminal Out, an MOSFETQE1 of an enhancement mode for program is inserted between the terminal Out and an earth, and another enhancement mode MOSFETQE2 is inserted between the terminal Out and the earth. Furthermore a pulse generating circuit 10 which delivers the pulse signal of a prescribed pulse width of level 1 after the application of a power supply is provided along with a latch circuit 20 which stores the signal of the terminal Out. With such an IC, the current flows to the element F as long as the element F is not fused only when the pulse signal is applied to the MOSFETQE2 from the circuit 10 to turn on the MOSFETQE2.

Description

[Detailed Description of the Invention] Technical field 1 of the invention This invention relates to a semiconductor integrated circuit having a large capacity to switch to a backup circuit when the regular circuit is defective. The present invention relates to a semiconductor integrated circuit that generates a signal used as a switching control signal when switching a circuit.

Technical Background of the Invention Recently, in semiconductor integrated circuits and sometimes semiconductor memories,
A regular memory cell circuit and a spare memory cell circuit are formed in advance, and if there is a defective bit in the regular memory cell circuit during manufacturing, this defective bit part is replaced with a spare memory cell circuit. There is an increasing number of devices that have a great mourning function, such as those used for personal use. This is because even if a normal memory cell circuit has just one defective cell, the memory as a whole is defective, so such memories are discarded as defective products. However, as memory capacity increases, the probability of defective memory cells occurring increases, and if defective memory is discarded, the cost of the product becomes extremely high. Therefore, in order to improve the overall yield, a method has been adopted in which a spare memory cell circuit is formed and used as a substitute when a part of the regular memory cell circuit is defective.

Information for switching is written in a non-volatile memory element.

FIG. 1 is a block diagram of a semiconductor memory in which the above-mentioned spare memory cell circuit is formed.

In FIG. 1, it is an address buffer to which a 1ri address signal is applied, and the output from this address buffer 1 is applied in parallel to a regular address decoder 2 and a spare address decoder J4C. The decode output of the regular address decoder 2 is given to the regular memory cell circuit 4, and one or more memory cells in the regular memory cell circuit 4 are selected by this decode output,
Thereafter, the data stored in the selected memory cell is read out. Further, the decoding operation of the regular address decoder 2 is controlled by the output from the spare address decoder S. The decoded output of the spare address decoder 3 is given to the spare memory cell circuit 5, a memory cell in the spare memory cell circuit 5 is selected by this decoded output, and data is then stored in the selected memory cell. The 99 data is memorized and extracted. Further, the output of the spare address decoder 3 is also output as a signal for controlling the decoding operation of the regular address decoder 2. Furthermore, in the decoding operation of the spare address decoder S, if there is a defective bit in the regular memory cell circuit 4, this defective part is replaced with a memory cell in the spare memory cell circuit s.
K.

The ninth information of the memory cell circuit is controlled by an exchange control signal outputted from an exchange control signal generator 6, which is written in advance in a nonvolatile memory element. That is, in a semiconductor memory having such a configuration, if there is no defective bit in the regular memory cell circuit 4, the exchange control signal is not output, and only the regular address decoder 1 operates to replace the memory in the regular memory cell circuit 4. A cell is accessed. on the other hand,
If there is a defective bit in the regular memory circuit 4, the spare address decoder S is programmed in advance so that a decode output corresponding to the row or column address containing the defective bit can be obtained, and the replacement control signal generator is also programmed. The non-volatile memory resistor 7 is programmed so that a level or 0 level exchange control signal can be obtained from φ. Therefore, the address no. When an output corresponding to a row or column address including a defective bit is obtained, a memory cell in the spare memory cell circuit 5 is selected by the spare address decoder S.

Furthermore, the decoding operation of the regular address decoder 1 is stopped by the decoded output of the spare address data 1 at this time, and the regular address data cell circuit 4 is not accessed. Cell circuit 4
The defective portion within is replaced with a spare memory cell circuit 5.

FIG. 2 is a circuit diagram showing a conventional configuration of the exchange control signal generating section 6. As shown in FIG. In the circuit shown in FIG. 2(a) K, a phase element r made of polysilicon, which is one of the nonvolatile memory elements, is inserted between the power supply VD application point and the output terminal Oat.

Insert the program enhancement %-)”0M08FIi?QB between the output terminal Oat and the ground point,
And there is a dip l between the output terminal Out and the ground point.
MO1iFW in mode? Insert Qi, ? M, O'8
The gate of ff E T=Q,' has a Gudaram signal P.
t- is applied, and the gate of MO8FITQ1) is connected to the ground point. It was. In the circuit shown in Fig. 2(b) K, an enhancement shade MO8FETQI for programming is inserted between the power supply VD application point and the output terminal Oat, and a depression effect is similarly inserted between the power supply VD application point and the output terminal Out. Insert MOIIFI〒QD in mode mode, insert a phase element r between the output terminal and the ground point, give the program code P to the gate of MO8FITQ, and connect the gate of MOgFlTQn to the output terminal OmtK. It was designed to do so.

In the circuit of FIG. 2(a), if the 7-use element T is not fused, the level of the output terminal 011t is M@t.
Fl: is maintained at a level depending on the resistance ratio between '1Y (4D) and the element r. on the other hand.

M @g F11'r (When Lebel's program signal pt is applied to the gate of 44m, this MO!IFITQ turns on and a large current flows through the phase element FK, and this 1&
7 due to the jiguru fever that occurs! L-Z element r is fused. When the phase element r is blown out, the % signal P becomes 0 level again and the MOIIF is cut off.
This time, the output terminal Out is discharged to the O level via MOgFlTQn. Then, when the level of the signal at the output terminal Oat, that is, the exchange control signal, is at level 9, for example, l, the decoding operation of the spare address decoder 1 is stopped, and the decoding operation is performed at level 9, for example, 0, and 1i. .

Figure 2 (In the circuit of Xun, contrary to the circuit of No. 21f(a), when the phase element ? is not fused, the output terminal O
The level of ut is MO8FICTQD and 7z - (Depending on the resistance ratio with element r, phase element y is blown out in the same way as in the case of 0 Léperny, and then the output terminal Oat becomes MOI
Rebel is charged via FITQD. In this case, when the level of the signal 4t1 of the output terminal Out, that is, the level of the exchange control note, is 9, for example, the O level, the decoding operation of the spare address decoder 3 is stopped, and the decoding operation is performed when, for example, it is the level.

FIG. 8 is a circuit diagram showing an example of the configuration of one decoding circuit of the spare address decoder S. Is this circuit a MO8FI with depletion mode for the load? Qt,n
and each address signal M, M, output from the address buffer 1.

AI+11...An 7Aze element Fl.

In a decoding circuit like Jin, for example, among the memory cells of the regular memory cell circuit 4, address A,=A
, z-...Shinmu m = OK If the corresponding one is Sennari, each of the 7A's elements Pg is programmed so that a decode output corresponding to this address is obtained, that is, Mu, , Mu,・・・−・M with Muho as gate input
Ofl, 7A element connected to FETQo*?
, is fused.

Problems with the Background Art In the conventional switching control signal generator shown in FIG. The flow is now in good condition. On the other hand, this 7Aze element r is fused and 1
The width of the pattern shape is made extremely narrow in order to make it more compact. This rounding is unfavorable in terms of reliability since the above phase element PK constantly flows a current.For example, the power supply TDK noise was caused by some reason, or the power supply voltage was increased by mistake. In such a case, an abnormal current may flow through the 7Aze element 1 and it may be erroneously blown out.

Purpose of the Invention Therefore, the purpose of the present invention is to obtain a binary output t- using a non-volatile memory element.
It is possible to provide a semiconductor integrated circuit t11 with high IIIll performance.

Summary of the Invention The semiconductor integrated circuit of the present invention includes a non-volatile memory element such as a phase element whose impedance changes non-volatilely between both ends, between a power supply and an output terminal, and a relationship between the output terminal and the ground KMOIIFICT. By inserting a switching element, switching the switching element for an initial period after power is applied, and storing the signal at the output terminal during the period when the switching element is switched, the non-volatile memory element can be stored. Even when the impedance between both ends is low, it is possible to improve reliability by obtaining an output of 2 ll without having to constantly supply current to this nonvolatile memory element. .

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings. FIG. 4 is a rounding circuit diagram explaining the invention in detail. This circuit has a fuse element Ft made of polysilicon between the power supply VD application terminal (one end of the potential supply) and the output terminal Out, and a fuse element Ft made of polysilicon between the output terminal Owl and the ground (the other end of the potential supply end). Insert MO8FKTQmt in enhancement mode for programming and output terminal O
Insert another enhancement mode MO8F CTQzz between ut and ground, and store the pulse generation circuit J0 that outputs a pulse signal with a predetermined pulse width of Lebel after the power is turned on, and the signal of the above output terminal Out. A latch circuit 20 is provided, and the program signal P is applied to the gate of the M08FETQE1, and the pulse signal output from the pulse generation circuit 10 is applied to the gate of the KMO8FETQv*. The output of the latch circuit 20 is applied to, for example, a spare address decoder S in the circuit shown in FIG.

In such a circuit, when the fuse element F is not blown, current flows through the seven-use element F from the pulse generating circuit 10 to MO! This is when a pulse signal is given to IFETQΣ and this MO8FETQz* is turned on. Therefore, since current does not constantly flow through the 7-use element FK as in the prior art, v14 does not melt and the reliability can be increased. t, fuse element? The information as to whether the MO8FETQx is fused or not, that is, the information on the program, is reliably output because the latch circuit 20 stores and holds the signal of the output terminal Out when the MO8FETQx is on. In addition, MO8
FICT4bt is used to blow out the 7-use element F, as in the prior art, and is given a program signal P which is at the Kl level when f# is off.

Figure 1s5 is a circuit diagram showing the configuration of an embodiment of the present invention, in which the pulse generating circuit 10 includes a resistor 11 and a capacitor lj inserted in series between the power supply VD and the ground;
It is composed of an inverter 11 that inverts a signal at a series connection point between these resistors 11 and a capacitor 12, and the inverter rsolfr force is applied to the gate of MOllFET QEm. Further, the latch circuit 20 has an output terminal Out.
A flip-flop 2J consists of a pair of NOROR gates 2jlM whose inputs are the signal of It consists of M08FETQ3 in enhancement mode.

In such a configuration, when the power supply VD is turned on and a potential difference of VD is applied between VD and the ground, immediately after that, a pulse signal having a predetermined pulse width of Lebel is output from the inverter IS. Then, M08FETQE is turned on for a predetermined period. At this time, if the 7-use element F is not fused, the output terminal Out becomes a level. Therefore, NOR
The output of gate 2 is 0 level MO8FIT
Even after the on-period of QE ends, the output terminal Out is kept at the level by the fuse element F, so the output of the NOR gate 37 remains at 0 level and does not change.

On the other hand, phase element F is set in advance by M08FETQE1.
When 1M08FK'rQEl is turned on while 1M08FK'rQEl is fused, the output terminal Out is discharged to the 0 level. At this time, the output of the NOR gate 22 is at the 0 level due to the level output from the inverter 7J, so the NOR gate The second output of 21 is the end of Lebel. The M08FETQzs is turned on by the level output of the NOR gate 21, and thereafter, the output terminal Ot+t is held at the θ level by the MO8FKTQms. Even if the output of the inverter 3 returns to 0 level, the output of the NOR gate 21 is maintained at the level.

In this way, in the circuit of the above embodiment, a level signal or a θ level signal is output depending on whether or not the fuse element F is blown after the power is turned on.

FIG. 6 is a circuit diagram showing the configuration of another embodiment of the present invention, which differs from the circuit of the above embodiment in the configuration of the latch circuit 20. That is, the latch circuit 20 includes two inverters 24 and 25 connected in series, and an enhancement mode MO8 inserted between the input side of one of the inverters 24 and the output terminal Out and used as a transmission gate.
FETQz+ and an enhancement mode M08FETQEB inserted between the input side of the inverter 240 and the output side of the inverter 25 and used as a transmission gate.
and another inverter 26 that inverts the output direction of the inverter J3 in the pulse generating circuit IO.
The output of the inverter 13 is applied to the gate of 8FETQE4, and the inverter 26 is applied to the gate of MO8FETQ.
The output of each is given.

In such a configuration, during the period when the pulse signal of Lebel is output from the pulse generation circuit 1°, the MO8FET
Qza is turned on, and the signal at the output terminal Out is set to the θ level or level depending on the state of the 7-use element.

At this time, since M08FITQg4 is also turned on, the signals at the output signal Out are sequentially inverted by the inverters 24 and 25, and the output terminal O is output from the inverter 25.
Assuming that the output period of the 0-order pulse signal in which the ゛ signal of the same level as ut is obtained ends, MO8FETQE4 is turned off, the input side of the inverter 24 is separated from the output terminal Out, and this time 1tl (JSF'' ETQE is turned on and the output of inverter 25 is this MO8FETQ.
Since the signal is returned to the input terminal of the inverter 24 via the inverter 25, the output of the inverter 25 is held at the same level as the signal up to t.

Therefore, in this embodiment circuit as well, a level signal or an O level signal is output depending on the state of the fuse element F after the power supply VD is turned on.

FIG. 7 is a circuit diagram showing the configuration of still another embodiment of the present invention. This embodiment circuit consists of the circuit portion of the embodiment circuit shown in FIG. 5 except for the pulse generation circuit 10 and the latch circuit 20, that is, the MO8FETQEteQE! The relationship between the power supply VD and the ground of the circuit portion consisting of the fuse element F and the fuse element F is reversed. In this case, MO8FiTQz
s is inserted between the output terminal Out and the power supply VD application point, and the output of the NOR gate 21 is applied to the gate of this M08FETQE3 via an inverter 27. The output signal level of the NOR gate 21 in this case is the opposite level to that of the embodiment of FIG. 5 for the same state of the fuse element F.

Note that the present invention is not limited to the above-mentioned embodiments; for example, the case where the fuse element F is fused using a MOFET QEI has been described; and in this case FiMO8FETQzx
is not necessary. Furthermore, instead of fuse element F, KMNO8
, FAMO8 or the like may be used, and any element whose impedance between both ends can be changed in a non-volatile manner can be used in place of the fuse element F.

When using a 7:L-Z element made of 9-polysilicon, the initial state is made into a resistive state so that it is in the same state as when it was fused, and then laser annealed to lower the resistance. The state may be the same as the state without it.

Further, the pulse generating circuit J0 may be a circuit with a voltage difference/i2 shown in FIG. 8, which does not impose any conditions on the rising power of the power source VD.

As described in detail, according to the present invention, it is possible to provide a highly reliable semiconductor integrated circuit that can obtain a binary output using a nonvolatile memory element.

[Brief explanation of the drawing]

Figure 1 is a block configuration diagram of a semiconductor memory in which a spare memory cell circuit is formed, and Figures 2 (a) and (b) are the conventional configurations of some of the circuits of the 1,4-body memory described above. FIG. 8 is a circuit diagram showing the configuration of other parts of the semiconductor memory, FIG. 4 is a circuit diagram for explaining the invention in detail, and FIGS. FIG. 8 is a circuit diagram showing the configuration, and is a circuit diagram showing another example of the pulse generation circuit in FIG. 8 uFiM4. ! ...address buffer, F...regular address decoder, 3...spare a)° address decoder, 4...
Regular memory cell circuit, 5... Spare memory cell circuit, 6... Exchange control signal generator, Qz e Qnm,
□Qwl-Qzm...Enhancement mode MO8FET* QDI QLD"...Dipleg mode MO8FET, F, Fl...phase element, 10...pulse generation circuit, 20...latch circuit , 11...Resistor, 12...Capacitor, 1
3,24°25, :16,27...Inverter, xx
, xx...NOml'-to, II3...Flip 7
Takehiko Suzue, Patent Attorney, Applicant's Representative
1 Yugong ^

Claims (1)

[Scope of Claims] (1) A non-volatile memory element inserted between one potential supply end and the output end, in which the impedance of the first pixel link changes in a non-volatile manner; a switching element inserted between the upper i-pi and the other potential supply terminal, and means for switching the switching element during a period during which a predetermined potential source is applied between one and the other potential supply terminals, or during a period of use after being applied; and means for storing a signal at the output terminal during a period in which the switching element is switched. (2) The semiconductor integrated circuit according to claim 1, wherein the nonvolatile memory element is a 7A resistor whose thickness is lowered by polysilicon. (8) Ii! The I-era semiconductor integrated circuit is formed in a semiconductor memory that includes a regular memory circuit and a spare memory circuit, and when a defective memory occurs in the regular memory circuit, the defective memory is replaced with the memory in the spare memory circuit. 2. The semiconductor integrated circuit according to claim 1, wherein a signal from means for storing a signal at the output terminal is used as an exchange control signal used for the exchange control signal.