JPS58105657A - Pcm signal transferring system - Google Patents

Abstract

PURPOSE:To realize a transfer of PCM signals having a high capability of transferring distance, by providing synchronizing sections whose modulation rule is broken for detecting synchronism and always generating level inverted sections of one bit portion just after the synchronizing section. CONSTITUTION:A PCM signal is inputted into a gate 1, and at the gate 1, the one bit portion of the PCM signal just after a synchronizing section is set to ''0'' and the one bit portion is logically multiplied by a gate signal for providing level inverted sections, and then, the output is ORed by a transferring clock (c) and a gate 2 and becomes the input of one side of a gate 3. The other input of the gate 3 is a synchronizing gate signal (d) and its output (e) is inputted to a flip-flop F/F4. The clock input (f) of the F/F4 has a double speed of the transferring clock, and in case the clock is inputted when a JK input is ''1'', the output is inverted, but the output is not inverted when the JK input is ''0''. Therefore, the output of the F/F4 becomes one shown by (g) of the diagram, and passes through a driver 5 and delivered to a transmitting terminal 6.

Description

[Detailed Description of the Invention] This invention is a PCM that samples and quantizes analog signals.
This relates to a signal transfer method.

Conventional data transfer methods include a method in which, in addition to data transfer, a transfer clock and a sampling period clock are also transferred, and a method in which data is modulated and transferred using a single data line. Especially for the latter, as the filling information of the sampling period,
There are (A) a method in which the synchronization pattern shown in FIG. 1 is added to each period for modulation, and (B) a method shown in FIG. 2 in which a synchronization section that violates the modulation rule is generated in each period. However, here, as an example, the modulation rule is the B1-phase method. The method (A) requires a pattern matching circuit to detect the synchronization pattern on the demodulation side, and there is also a risk of detecting the sampling period when a pattern identical to the synchronization pattern occurs in the data. Furthermore, the method (B) has the disadvantage that by breaking the modulation rules, the frequency band required for transfer is expanded and the data transfer ability is reduced.

This invention was made to eliminate the above-mentioned drawbacks, and FIG. 3 shows transfer waveforms according to one embodiment of the invention. In the figure, the first bit of the data shown in FIG. 3(a), which is data before Vi modulation and corresponds to immediately after the synchronization period, is always fixed to "0#".

Figure 3 (1)) modulates the data in Figure 3 (→) using the B1-phase method and adds a synchronization interval (an interval in which there is no change point equivalent to 4 pits), which is a PCM signal transfer. This corresponds to the transferred waveform.As can be seen in Fig. 3(b), l [vk in a state where there is no change point corresponding to 4 pits is such that a state g (level inversion section) in which there is no change by 1 pit occurs. Examples of transfer waveforms are shown in Figs. 4 and 5. Fig. 4(a) is a diagram of received waveforms due to transfer according to the present invention, and Fig. 4<b) is a diagram of its reproduced signal waveforms. Figure 5 (a)
Figure 5 (b) is a received waveform diagram when the bits immediately after the synchronization interval are transferred in a configuration that does not impose any restrictions, and is a reproduced signal waveform diagram. It is clear that if the switching occurs after 5 pits, a multiplication noise will occur. Fig. 6 shows a transmitting circuit diagram for forming a transfer signal according to the present invention, Fig. 7 shows its time chart, Fig. 8 shows a receiving circuit diagram for receiving the transfer signal, and Fig. 9 shows its timing chart. A time chart is shown.

First, the transmitting circuit will be explained. The PCm message to be transmitted in Figure 9pJ6 is shown in Figure 7(a) and input manually to AND gate (1). Here, one pit immediately after the synchronization period, which is the timing of this invention, is set to 10# and is ANDed with the gate signal (same figure (off)) for providing a level inversion period, and the output data of the AND gate (1) is The transfer lock shown in Fig. 7 (0) and the OR gate (2) combine to form one side of the AND gate (3).Stutter 1
The other human input is the synchronous gate signal shown in FIG. 7(d).

Output of AND gate (3) (Figure 7(e)
)) manually inputs the flip-flop (4) to J. J-
The tarock power of the flip-flop is twice as fast as the transfer lock shown in FIG. 7(f). The 7 lip-flop (4) in J, performs the previous work in which the output is inverted when the clock is input when the human power is "11" in J, and the output does not change when the human power is #010 in J-.

Output (g) of 7 lips and 70 tubes (4) to J- (Fig. 7 (
g)) is sent to the transmission terminal (6) through the driver (5). Next, the receiving circuit will be explained. In figure 8, the human power from the receiving terminal (7) is waveform-shaped by the receiver (8), resulting in the state shown in figure 9 (h). Receiver (
The output of 8) is inputted to the D-type flip 70 tube (9), which is manually inputted to the treacherous OR circuit (11), to create the edge signal (1) of the received data (Fig. 9 (1)). . The edge signal (1) is input manually to a multi-pie break (12) set to a holding period of 0.75 pits, and this output is a transfer lock and is output to a terminal (16).

On the other hand, the inverted output (j) (Fig. 9 (j)) is a D-type flip 7.
It becomes the clock for 0 (9) and (1 (1)) and transfers the received data (h) to 1.

D type 7 lip 70 tube t9), output (1) of (10)
(k) (Figure 9 (1), (k)) The Fi transgressive disjunctive OR circuit 13) becomes human power, and the transgressive - logical sum circuit (13
)'s output (→ (Figure 9 (m)) is manually input to the D-type flip 70 tube (14). The inverted output (n) of the D-type flip 70 tube (Figure 9 (n)) is input to the demodulated data. It corresponds to the output layer (15).On the other hand, the synchronization period has a retention period of 3
It is detected by manually inputting the edge signal (1) to the retrigger gable one-shot multi-pie break (17) set for the bit, and the output (0) ((0) in Figure 9) becomes the sampling synchronization clock. Output to the pharynx (18).

As described above, we created a synchronization section that violates the modulation rules for synchronization detection, and created a configuration that always generates a level inversion section for one pit immediately after the synchronization section, so the transmission distance can be reduced without increasing the circuit size. It becomes possible to transfer PCM signals with high performance.

In the above embodiment, the synchronization period is set to 4 bits, but any number of points may be used as long as it is 2 or more bits.

Further, in the above embodiment, the B1-7 method was explained as a transmission line code, but this is not strictly defined, and the level inversion section immediately after the synchronization section always has a certain length. It may be configured. In addition, modulation methods include PK modulation M F' M modulation, ZM modulation, /FMf modulation,
415M N RZ I modulation, 3PM modulation, etc. may also be used. - For example PE modulation (# LIOW for “1”
The configuration is such that the level changes from a to 'H1gh' level, and from 'H1gh' to 'LClv' level for 101, and a level change at 4 o'clock occurs at the transition point of the pit so as to satisfy the above rule. ) transfer waveform example as the first υ
The figure shows an example of the transfer waveform of MFM change, , 11 (for '11, a level change occurs, and for 101, a level change occurs at the pit change only when 10' continues). As shown in the figure. Here, select the longest level inversion interval in the modulation rules as the level inversion interval immediately after the synchronization interval.
In the case of modulation, it is equivalent to one pit, and in the case of MFM modulation, it is equivalent to two pits.

[Brief Description of the Drawings] Figure 1 shows a PCM signal transfer waveform in which a synchronization pattern is added to each synchronization as information for conventional sampling synchronization, and Figure 2 shows a modulation rule as information for conventional sampling synchronization. FIG. 3 is a diagram showing an example of the PCM signal transfer waveform according to the present invention, and FIG. 4 (fL), (1)) is the PCM signal transfer waveform according to the present invention. Diagrams showing the demodulated signal waveforms, FIGS. 5(a) and (k
l) is a diagram showing the PCMyi signal transfer waveform and its demodulated signal waveform according to the conventional example, FIG. 6 is a transmitting circuit diagram according to the present invention, FIG. 7 is a diagram showing its time chart, and FIG. 8 is a diagram according to the present invention. 9 is a diagram showing a time chart thereof, FIG. 10 is a diagram showing an example of a transfer waveform when this invention is applied to PM modulation, and FIG. 11 is a diagram showing this invention in MFMj (
FIG. 3 is a diagram showing an example of a transfer waveform when applied to a word. In the figure, (1), (3) Fi and gate, (2
) is the OR gate, (4) f-4; f, flip 70 knob, (5) is the driver, (6) is the transmitting terminal, (7) is the receiving terminal, (8) is the receiver, (9) , (10 ), (
14) is a D-type flip-flop, (11), (13)
ii The irreversible OR circuit (12) is a one-shot multi-pie break, (15), (16), (18) u output layer elements, and (17) is a retriggerable one-shot multi-pie break. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Makoto Kuzuno - Procedural Amendment (
Voluntary) Commissioner of the Japan Patent Office 1, Indication of the case: Japanese Patent Application No. 86-104677 2, Title of the invention: PCM signal transfer method 3, To the representative Hitoshi Katayama of the person making the amendment: 4, Attorney 5, Specification subject to amendment In the Detailed Description of the Invention column and Drawing 6, contents of amendment (1) "PE modulation MFM modulation" on page 8, line 4 of the specification is corrected to "PE modulation, MFM modulation." (2) Figures 4 and 10 of the drawings will be corrected as shown in the attached sheet. 7. List of attached documents (11 drawings (Fig. 4, Fig. 10), at least 1 copy each)

Claims (11)

[Claims] (1) When transmitting a PCM signal by modulating it into a transmission signal according to a predetermined modulation rule, a direct period that does not follow the above modulation rule is provided at regular intervals, and A PCM signal transfer method characterized by providing a level inversion section. (2) The PCM signal transfer method according to claim 1, wherein the length of the level inversion section is set to be shorter than the longest level inversion interval realized by the modulation rule. (3) The PCM signal transfer method according to claim 1, wherein the length of the level inversion interval is set to the length of the longest level inversion interval realized by the modulation rule. (4) The PCM signal transfer method according to claim 1, wherein the synchronization interval is set to be longer than the longest level inversion interval realized by the modified 11fiL rule. (5) The PCM signal transfer method according to claim 1, wherein a synchronization period is provided for each sampling period. (6) The PCM signal transfer method according to claim 1, wherein the length of the level inversion section is made to be the same length as the longest level inversion interval realized by the modulation rule. (7) A PCM signal transfer method according to claim 1, wherein the modulation rule is the B1-7 method, and the first bit of the level inversion section is set to a level equivalent to 10#. . (8) The PC according to claim 7, wherein the signal within the synchronization period is at the same level over a plurality of bits.
M signal transfer method. (9) The modulation rule is the pg system, and the first two bits of the level inversion section are set to a level equivalent to '0.1' or '1,0'. PCM signal transfer method. (10) When the signal in the synchronization interval has the same level over multiple bits and the level is 'high', the first two pits of the level inversion interval are at the level equivalent to '0, 1', and the level 10. The PCM signal transfer system according to claim 9, wherein the first two pits of the level inversion section are at a level corresponding to #1.0# when the signal is 'Low'. (11) The modulation rule is MFM modulation method, ZM modulation method, M
2FM modulation method, 415 MN RZ I gy4
The PCM signal transfer method according to claim 1, which is any one of the method-1 3PM modulation methods.