JPS5811073Y2 - digital setting receiver - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a digital setting receiver that can perform channel selection digitally.

In an AM or FM radio receiver of the type that selects a channel by changing at least the local oscillation frequency using a control voltage, mechanical operations such as turning a variable capacitor as in the conventional art are, of course, unnecessary.

In addition, if the control voltage is generated by a sweep voltage generator and the sweep is stopped when the desired reception frequency, that is, the broadcast signal is received, pure electronic control of channel selection becomes possible.
Furthermore, by providing a digital setting device and a comparator to specify the receiving frequency, it is possible to automate the detection of the desired frequency, stop of the sweep, or tune selection, and select any desired broadcasting station simply by changing the settings of the digital setting device. becomes possible.

To digitally specify this receiving frequency, the broadcasting frequency can be directly converted into BCD (Binary Coded Decimal).
It is also possible to express the signal as a code (mal) -y-, but this method requires 12 or 10 bits and complicates the comparator, frequency setter, etc.

The present invention aims to improve the problem of peeling and to enable setting with a small number of bits, thereby simplifying and reducing the cost of the receiver.

Furthermore, according to the present invention, it is possible to change the sweep speed and sweep at a high speed until the tuning point is approached, and then at a low speed when the tuning point is approached, thereby ensuring reliable channel selection.

The digital setting receiver of the present invention is equipped with a counter for frequency division and a counter whose complement is preset, and counts the output frequency of the local oscillator of the radio receiver. a counting circuit that generates an output that gradually increases every time, and a digital setting device that sets an arbitrary reception frequency that becomes 1 at the lower limit of the broadcasting frequency band and gradually increases every fixed frequency width corresponding to the output; A digital setting receiver comprising a digital comparator which receives the outputs of the frequency divider and the setting device and produces an output that gradually increases or decreases the output frequency of the local oscillator until the two match, wherein the comparator is configured to input the output frequency of the local oscillator. The output frequency of the local oscillator is gradually increased or The present invention is characterized in that it includes a digital comparator that sweeps the gradually decreasing output at high speed until it approaches the tuning point, and at low speed when it approaches the tuning point, which will be described in detail below with reference to the drawings.

FIG. 1 shows the main structure of a receiver according to the present invention.

Reference numeral 10 denotes an input terminal into which the local oscillation frequency LOF of the AM or FM receiving section is input.

1 is a decimal counter that divides the input frequency.

2 is a ternary counter when receiving AM, 4 is a counter that is finally switched when receiving FM, and 3 is a counter that is preset with the complement of the pulse count value from zero until entering the broadcast frequency band, and outputs a count of 1 only after entering the broadcast frequency band. This is a presettable counter.

4 and 5 are comparators, and the upper bit group Bus of the BCD value of the desired broadcasting frequency is set by the digital setting device 6.
and the lower bit group BIS are input, and the counter 2
, 3, the upper bit group Bua and the lower bit group Bla of the broadcast frequency are inputted, and these are compared and the result is inputted to the output control section 7.

Reference numeral 9 denotes a voltage storage element which, when receiving a positive or negative voltage from the output control unit 7, outputs a voltage that increases or decreases in proportion to the input time, and when the input voltage is stopped, the output voltage changes. It is known to have a long-term memory function.

Figure 2 shows details of the main parts of Figure 1, and in this figure C1 to C
8 is a counter, among which counters C3 and C4
and C5, C6 to C8 correspond to counters 1, 2.degree.3 in FIG.

Further, CP1 and C20 are comparators and correspond to figures 4 and 5 in FIG.

The output control section 7 in FIG. 1 has a large number of diodes D as shown in FIG.

~D13, resistors R1 to R7, transistor Tr3. Tr
Consists of 4 parts.

The counters C1 and C2 are decimal counters, and divide the local oscillation frequency FML of the FM receiving section applied to the input terminal Ta into equal parts and apply it to the Nantes gate G1.

On the other hand, the local frequency AML of the AM receiving section applied to the input terminal Tb is directly applied to the Nantes gate G1.

Trl and Tr2 are switched by adding these AM and divided FM local oscillator frequencies, and the Nant gate G1
This is a transistor that provides input to the

Next, the operation of this device will be explained. First, the listener uses the digital setting device 6 to set the frequency of the broadcast station that he or she wishes to receive.

On the other hand, the receiver's local oscillator output frequency LOF (AML,
A part of FML) is sampled by the gate circuit G1 which is opened for a minute time by the gate signal Sg1, and the frequency is divided by the counters 1 to 3 (C3 to CS), and the frequency division ratio is selected as follows.

As is well known, in Japan, the local frequency is AM (520
~1600) +455 KHz, FM (76
~90) -10.7 MHz, so the gate signal S
The Nant gate G1 is opened for 1 ms by gr, and the AM local oscillation frequency remains as it is, and the FM local oscillation frequency is set at the counter C.
1, C2 divides the frequency by h and samples, from the Nant gate G1, for each sampling, there are +455 pieces for AM (520 to 1600), and +455 pieces for FM (76
00-9000) -1070 pulses are output.

The decimal counter C3 divides this frequency into 100%, so one output pulse is IOK for AM and 100 for FM.
The output of this counter C3 is the domestic A
M, FM broadcasting frequency classification unit 10K f-1z,
Compatible with 100 KHz.

Next, the output of the counter C5 is fed back to the counter C4 via the gate circuit (Nant gate) G2, and when this gate circuit is opened by the signal Sg3, the feedback disappears and the output of the counter C5 is fed back to the counter C4 via the gate circuit (Nant gate) G2. When the gate circuit is closed by the signal Sg3, the feedback circuit becomes a ternary counter.

In this device, when it is AM, the gate circuit G2 is closed and it becomes a ternary counter, and when it is FM, the gate circuit G2 is opened and it becomes a quaternary counter.

Therefore, the output of these counters will be every 30 KHz for each pulse in AM, and every 400 KHz in FM.

The presettable counters C6 to C8 count the output pulses from the counter C5 and indicate the reception frequency, but if you simply count them, you only need to indicate the reception frequency band, but they count and display unnecessary parts up to the reception frequency band. This is uneconomical.

Therefore, the counters C6 to C8 are connected to the preset number input device PI.
A predetermined number is preset by , so that when there is a person in the reception frequency band, the count value becomes the initial state of OO...01.

This preset number is determined as follows. That is, the number of input pulses to this counter is 33 to 69 pulses/time in AM,
In the case of FM, it is 163 to 199 pieces/time, and the width is 36 in both cases.

To get 1 after counting 33 or 163 pieces, use 3
It is sufficient to set the complement of 2 or 162 in the counter in advance.

Now let's assume that the number of bits in the counter is 9 bits and it is 1000000.
If you subtract the BCD value of 32 or 162 from 00, the difference is 0.
11100000 or 001011110.

The broadcast frequency range is equivalent to 36 output pulses of counter C5, and the BCD value is 6 bits, so there is no need to provide a counter that can set the above difference as is, and the counter can be set as 6 bits. The last six digits of the above difference may be preset to 100000 or 011110.

In this way, by inputting 100000 for AM and 011110 for FM into the 6-bit counters C6 to C8 using the preset number input device PI, the output starts from the initial state of 000001 when entering the broadcast frequency band, and from then on
0000 every 30 KHz on FM, every 400 KHz on FM
010.0000011.0000100...
and 10010, which corresponds to the upper limit of the broadcast frequency band.
An output that steps up to 0 is obtained.

Comparator CP2 outputs the top four outputs of counters C6 to C8.
(Pitsu) F, E, D, and C are input, and the lower two bits B and A are manually input to the comparator CP1.

The unit of broadcasting frequency is 10 KHz in AM as mentioned above.
, Since FM is 100 KHz, counter C
6-C8 output pulse AM every 30 KJIz, FM
At every 400 KHz, three or four frequency units (ie, broadcast stations) are included between each pulse.

To distinguish this, counters C5 and C are connected to comparator CP1.
4, the lower two bits A2 and A1 are further input.

As a result, comparator CP1. The reception frequency signal input to the CP2 is as shown in Table 1 or Table 2 below, and this is also the BCD value of the desired broadcast frequency set by the digital setting device 6.

In these tables, the 1st to 8th digits are arranged in order from the lower digit to the upper digit, such as A, , A2 . A-F corresponds to this.

The 9th digit is for AM/FM identification used in digital settings, with AM being represented by 1 and FM being represented by O.

Comparator CP1. To explain CP2 and its operation, when the set frequency Fs by the digital setting device 6 is lower than the reception frequency Fa, the comparator CP2 outputs a high (H) level to its terminal ta and a low (L) level to its terminals tc and tb. arise.

It is led to the X conductor through the output diode D5 of the terminal ta, and causes the voltage storage element 9 to generate an output in the direction of lowering the local frequency.

In principle, this voltage storage element 9 is an integrating circuit, and when a positive input voltage is input, it is integrated to generate an output voltage that gradually increases, and when a negative input voltage is input, this output voltage is gradually decreased, and the input voltage is When turned off, the output voltage state at that time is maintained for a long period of time.

The L-level output voltage of the terminal tc of the comparator CP2 makes the diodes D9 and D10 conductive and outputs the output voltage of the comparator CP2.
1 output is locked to L level.

When the local frequency decreases due to the signal from the X conductor and becomes close to the set value, the output of the terminal ta of the comparator CP2 becomes L level, and the output of the terminal tc becomes H level, and the diodes D 9 and D 10 is made non-conductive.

As a result, the output of comparator CP1 becomes valid, and if the local oscillation frequency is still high, its terminal ta produces an H level output, which is led to the X conductor through resistor R2 and diode D6, and similarly This is a signal to decrease the number of firing points.

In this way, the local oscillation frequency further decreases, and eventually when it completely matches the set value, the terminal ta of the comparator CP1 returns to the L level.
The channel selection operation ends.

If the set frequency is higher than the local frequency, first comparator C
P2 outputs H level to terminal tb, and terminals ta,
An L level output is generated at tb.

As a result, an H level output is led to the Y conductor through resistor R8 and diode D8, which causes voltage storage element 9 to output a local frequency gradual increase command.

In this case as well, comparator CP1 outputs L level from terminal tC(7).
The output of is locked to L level, and when the local oscillation frequency approaches the set frequency, this lock is released and the output of comparator CP1 becomes valid, and when the local oscillation frequency exactly matches the set frequency, the channel selection operation starts. ends.

The reason why the comparison output is switched midway from comparator CP2 to C20 is as follows.

That is, since the comparator CP2 compares the upper bits, a difference between them means that the difference between the local oscillation frequency and the set frequency is large, and in this case, the local oscillation frequency may be changed rapidly.

This is done in the following manner in this circuit.

That is, when the output level of the terminal tc becomes L, the diode D1
□ becomes conductive, making diode D1□ non-conductive.

As a result, the signal Sgs is invalidated, and the transistor Tr4
During sampling with Nant gate G1 open and while resetting counters C4 to C8,
In other words, during the period when the contents of the counter fluctuate, the transistor T
Only the signal Sg4 that turns on r4 is added.

When transistor Tr4 is turned on, diode DI is turned on.

D2 becomes conductive and the H level outputs of the X and Y conductors are grounded, so local frequency control is interrupted.
Since the duty of signal Sg4 is 80%, this control interruption is suppressed to the necessary minimum of 20%, and control is performed at high speed.

On the other hand, comparator CP2 changes the output level of terminal tc to H.
When the diode Dll becomes non-conductive, the signal Sgs is applied to the transistor Tr4 through the diode D1□ of the OR circuit.

Since the duty of this signal Sgs is about 30%, the period during which the diodes D and D2 are on becomes long, and as a result, the local oscillation frequency is controlled at a low speed.

This is effective in preventing excessive control.

Diode D3. The circuit consisting of D4, resistors R5 to R7, and transistor Tr3 is a circuit for extracting a muting signal.
When there is an H level output on either the X or Y conductor, the transistor Tr3 is turned on and the muting signal Sg6 is turned on.
Output.

This is used to short-circuit the audio amplifier input signal and eliminate noise emitted from the speakers during tuning.

As described in detail above, according to the present invention, the set value and the received (local oscillator) frequency can be compared using 8 bits, and the comparator, setting device, etc. can be simplified.

Furthermore, since the upper 4 bits and the lower 4 bits are compared separately, the sweep speed can be lowered as the tuning point approaches, making it easy to perform channel selection without overdrawing.

Furthermore, various advantages can be obtained, such as muting during channel selection to enable channel selection operations with less noise.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a detailed circuit diagram of FIG. 1. In the drawing, 1 to 3, C1 to C8 are frequency dividers, 6 is a digital setting device, 4, 5. CP□, C20 are digital comparators.

Claims (1)

[Claims for Utility Model Registration] The output frequency of the local oscillator of the radio receiver is counted by a counter that is equipped with a frequency division counter and a counter whose complement is preset. a counting circuit that generates an output that gradually increases, and a digital setting device that sets an arbitrary reception frequency instruction value that becomes 1 at the lower limit of the broadcasting frequency band and gradually increases at a constant frequency thereafter in accordance with the output; and a digital comparator that receives the output of the frequency divider and the setter and produces an output that gradually increases or decreases the output frequency of the local oscillator until the two match, wherein the comparator is for lower bits. and one for the upper bits, and is configured so that the output of the comparator for the lower bits is blocked while the comparator for the upper bits produces a difference output, thereby gradually increasing or decreasing the output frequency of the local oscillator. A digital setting receiver characterized by being equipped with a digital comparator that sweeps the output at high speed until it approaches the tuning point and at low speed when it approaches it.