JPS58123762A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor device comprising a Darlington transistor.

Technical background of the invention and its problems A semiconductor device comprising a mesa-lid Darlington transistor usually has a circuit as shown in FIG. In the figure, 1 is a drive stage element consisting of an NPN II transistor. The emitter of drive stage element 1 is output stage element l
is connected to the base of the resistor 1.4 via a resistor 1.4. In addition, 5 in the figure is a protection diode. Also, the same figure) is.

It is a one-way diagram omitting a deception diode. This semiconductor device! The structure is as shown in FIG. 2 (transfer) to FIG. 2 (C). FIG. 2(2)) is a sectional view taken along the line BB in FIG. 2(4), and FIG. 2(C) is a sectional view taken along the line CC in the same figure (Company). In the figure, 10 is a collector layer of Nll. A P-type base layer 11 is formed on the collector layer 10 . In a predetermined region of the base layer 11, an Nll emitter 12 of the drive stage and an N-type emitter 11 of the output stage are formed at a predetermined interval from the Nll emitter 12 of the drive stage. A mesa groove 14 reaching the collector layer 10 is formed in the base layer 11 so as to surround the element region in which these emitters 11.11 are formed. In the mesa groove 14, a hole is formed. Furthermore, a drive stage base electrode 16 is formed on the base layer ll. A drive stage emitter electrode 11 is formed on the Nll emitter 1X of the drive stage so as to straddle the base layer ll, and a drive stage emitter electrode 11 is formed on the N type emitter lJ of the output stage so as to straddle the base layer 11. The output stage emitter electrode 18 is formed in this manner. Further, an oxide film 19 is formed on the exposed surface of the base layer 11.

In the semiconductor device 1 configured in this manner, the resistor 3 between the base layer 11 and the emitter layer 12 of the drive stage is usually formed by three-dimensionally utilizing the diffused resistance of the base layer 11. However, if this resistance value is too low, the direct current amplifier (hFIe) will degrade. In order to prevent this, it is necessary to set the resistance value of the resistor 3 as high as possible. For this reason, base layer 1. □ (The low resistance region only on the surface of 1 is not used for forming the resistor 1 as much as possible, and the shape of the current path between the base layer 11 of the drive stage and the base layer 11 of the output stage is formed by the mesa groove 14. In other words, by providing the extending portion 14a of the mesa groove 14 so as to narrow a predetermined area of the base layer 11 and the emitter layer 12 of the drive stage, the resistor 3 is connected to the emitter layer I2. The base layer II is formed directly below the base layer II.

However, the Darlington transistor has a wiring location that short-circuits the emitter and base, and the above-mentioned structure in which the mesa groove 14 is formed so that the N-type emitter, 2M base, and N-type collector junction are exposed, There is a drawback that the reverse breakdown voltage (VcBo) between the base and collector stagnates due to a short between the emitter and the base. An insulating film 25 is formed, and this insulating film 25
A semiconductor device sr is also manufactured in which an electrode z6 is formed to connect the base layer 11 of the drive stage and the emitter layer IS.
6, a step difference occurs due to the thickness of the insulating film 25.
There is a fatal drawback that breaks occur in the electrode wiring.

Note that FIG. 3(B) is a sectional view taken along line BB in FIG. 3(3), and %C) in FIG. 3 is a sectional view taken along line CC in FIG. 3(A).

In addition, the same parts as the semiconductor device snow viewing shown in FIGS. 2(4) to 2(Q) are designated by the same reference numerals.

OBJECTS OF THE INVENTION An object of the present invention is to provide a semiconductor device that improves the base-collector reverse withstand voltage of a drive stage element and prevents disconnection of electrode wiring.

Summary of the Invention The present invention forms an impurity region in the base length of the drive stage so as to face the extension of the mesa groove to increase the resistance value between the base and emitter of the drive stage element. This semiconductor device has improved collector-to-collector reverse breakdown voltage and prevents disconnection by providing electrode wiring directly on the base emitter layer of the drive stage.

Embodiment of the invention FIG.
The same figure (C) is a sectional view taken along the CC line of the same figure (roll). Go in the figure is an N-type collector layer. A base layer 11 of PIl is formed on the collector layer JO, which serves as the base of the drive stage element and the output stage element. base layer 3
1, an Nll emitter layer 3z of the drive stage and an Nll emitter layer 33 of the output stage are formed at a predetermined interval from the Nll emitter layer 3z. The base layer J1 includes ξ these emitter layers sz
, ss are formed, and a mesa groove 34 reaching the collector layer 10 is formed so as to surround the element region in which . Mesa groove 3
4 has an extending portion 34m extending so as to narrow the base layer S1 and emitter layer 32 of the drive stage. In the base layer 31 of the drive stage, N is provided facing this extension part 341 and at a predetermined interval from the emitter layer 3z.
A type impurity region 35 is formed. A protective film 36 is formed in the mesa groove j4. A drive stage base electrode J1 is formed in a predetermined area on the base layer 11.

A drive stage emitter'-pole 3a is formed on the drive stage emitter layer 32 so as to straddle the base layer 31. One output stage emitter electrode is formed on the output stage emitter layer 33. N-type impurity region S
S, base layer 1, and emitter layer 32. An insulating film 40 is formed on the exposed surface of j3. In the semiconductor device 41 configured in this way, the drive stage emitter electrode 38 connecting the drive stage emitter layer 32 and the base layer 31 is directly connected to the emitter layer. 32 and the base layer sl, it will not be cut off.

Further, a drive stage base electrode 31 is provided at a location that becomes the base input part of the drive stage, and an emitter layer 33 of the output stage is provided.
Since the output stage emitter electrode 3g which is in a shot state with the base layer 31 is provided on the top, the resistance value between the base and emitter of the drive stage element is determined by the drive stage base electrode 31 and the drive stage emitter electrode 38. layer 1
2, the resistance formed in the surface region between the impurity region 35 and the emitter layer Jz, and the resistance formed under the impurity region 35. The resistance R formed in the surface region between the emitter layer 32 and the impurity region 35 is determined by the roughness times the resistivity, and the width can be freely set depending on the photo-etching technique. As a result, the base-emitter resistance value of the drive stage can be set to a large value, and the base-collector reverse breakdown voltage can be improved.

Incidentally, the base-collector reverse breakdown voltage after forming the electrode wiring of the drive stage base electrode 31, drive stage emitter electrode 3#, output stage emitter electrode 39, etc. in a semiconductor device configured in this way (in humans) is as follows: As shown in Figure 5,
However, as shown in Figure 6, in conventional semiconductor devices, the electrode wiring becomes larger after it is formed than before it is formed, making it impossible to obtain stable device characteristics. I understand.

Next, a method of manufacturing a semiconductor device according to an embodiment will be explained with reference to FIGS. 7 to (2).

First, as shown in FIG. 7(4), a P-type base layer 31 was laminated on an N-type collector layer 10 by diffusing PM impurities into an N-type semiconductor substrate to a predetermined diffusion depth. Obtain the substrate. Next, Nli impurities are selectively diffused into a predetermined region of the base layer 31 to form an emitter layer 1z constituting a drive stage element, an impurity region 35 disposed facing a mesa groove 34 to be described later, and an emitter 1- of an output stage. 13 is formed.

Next, base layer 31% emitter layer 12, impurity region 3
After forming an insulating layer 40 covering the surface of 51, the same figure (II
), a window 40a is formed by photolithography in the insulating layer 40 corresponding to the area where the mesa groove is to be formed in the impurity region 35a, and the base layer 31 and emitter layer 32 are formed using the insulating film 40 as a mask. A mesa groove 34 having an extension portion 34m narrowing the groove is formed. Here, the depth of the mesa groove 34 is appropriately set so as to obtain a desired base-collector reverse breakdown voltage.

Next, as shown in FIG. 4C, a protective film 36 is formed of low melting point glass or the like in the mesa groove 34 using the insulating film 40 as a mask.

Next, as shown in ) of the same figure, the drive stage base electrode 1
7. A window 40b for forming the drive stage emitter electrode 38 and the output stage emitter electrode 1g is opened in a predetermined region of the insulating film 40. At this time, the insulation @is on the impurity region 35 facing the mesa groove j4 is not removed.

Thereafter, as shown in FIG. 3G, a drive stage base electrode 31, a drive stage emitter electrode 38, and an output stage emitter electrode 3g are formed to obtain a semiconductor device 41.

As described in detail, according to the method of manufacturing a semiconductor device according to the present invention, it is possible to improve the reverse withstand voltage between the base and collector of the drive stage element, and to prevent disconnection of the electrode wiring.

[Brief explanation of the drawing]

FIG. 1 (4) and the same figure) are circuit diagrams of a semiconductor device consisting of a Darlington transistor, FIG. 2 (4) is a plan view showing a schematic configuration of the device, and FIG. Figure 3 (4) is a cross-sectional view taken along the line B-B in the figure (4) is a cross-sectional view taken along the line C-C in the figure (2), and Figure 3 (4) is another conventional semiconductor device. The plan view of the same figure (B) is the same figure (4)
The cross-sectional view along line G1 in Figure 1, the value in the same figure) is C- in the same figure (G).
4(4) is a plan view showing a schematic configuration of an embodiment of the present invention, and FIG. 4(B) is a sectional view taken along line BB in FIG. 4(4). , the same value) is C- in the same figure (4)
A sectional view taken along line C, FIGS. 5 and 6 are characteristic diagrams showing the reverse breakdown voltage between the base and collector before and after the formation of electrode wiring, and FIG.
(4) to the same figure (the cranes are explanatory diagrams showing the manufacturing process of the semiconductor device of the example. 10... Collector R, It1... Base layer, 32...
...Emitter layer, 33...Emitter layer, j4...Mesa gourd J 4 m...Extension part, s s-...Im-
Area, ##-...Protective film, 11... Drive stage base electrode, 38... Drive stage emitter electrode, 39-...
Output stage emitter pole, 40-...insulating film, 40 m,
40 b・e*window, Ll...semiconductor device. Applicant's representative Patent attorney Takehiko Kage, ・□、、(Kidney aai (V) No. 6111!-1 is Zl...、、

Claims (1)

[Claims] A base layer of an opposite conductivity type formed on a collector layer of a conductivity type, a drive stage emitter layer and an output stage emitter layer of opposite conductivity types formed on the base layer with a predetermined interval, and a drive stage. a mesa groove formed to surround the base layer at a depth reaching the collector layer and having an extension portion that narrows the area of the emitter layer; 1. A semiconductor device characterized in that an impurity region of opposite conductivity type formed in a semiconductor device and a protective film formed in a mesa groove are odor-biased.