JPS5812663B2 - magnetic recording and reproducing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION In addition to the main track on which information signals such as audio signals and data signals are recorded, the present invention also records position signals for automatically searching and selectively reproducing the recorded information. Regarding a magnetic recording/reproducing device using a magnetic tape equipped with a position signal track, in particular, by changing the preset of a counter that counts the reproduced position signals, the number of addresses that can be specified is relatively increased, and the information (( The purpose is to perform the same control operation as the END signal recorded at the end of the information of the last address, which is the lowest search priority, for position signals corresponding to addresses greater than the maximum address that can be specified + 1). It is something.

That is, in the present invention, as a position signal indicating an absolute address, (K+i) (K is a positive integer) pulses are sent to address (i) corresponding to the address, and END of information is sent to the end of the information at the final address.
Record (K) pulses indicating the address desired for reproduction, set the corresponding storage means by an address designation operation corresponding to the address desired for reproduction, run the tape by a search command operation, and reproduce the position signal by counting. Then, a control signal for the tape running state is obtained by comparing and outputting the designated address number and the contents of the position signal counted by playback, and desired information is selectively played back, and means for switching the preset of the counter that counts the position signal. has 1 to n and END as means for specifying the address desired for reproduction, with END being the lowest search priority, and (n+i)
For a position signal corresponding to an address or higher, the same control operation as a position signal corresponding to an END signal is performed, and pulses whose number is less than the number corresponding to 1 of the address designation means are recognized as invalid pulses. However, when position signals corresponding to addresses from 1 to infinity arrive, they are selectively reproduced in response to address designation operations from 1 to n, and information corresponding to addresses (n+1) or more is output from the END of the address designation means. By controlling the PAUSE state by the specified operation to facilitate subsequent cueing and playback, and by switching the counter preset, the correspondence relationship between the memory address stored by the address specifying operation and the position signal counted for playback can be changed relatively. It is an object of the present invention to provide a magnetic recording and reproducing device that can double the number of addresses that can be specified.

The present invention will be described below with reference to the drawings.

In Figure 1, 1(1(1) to 1(n), 1(END
)) is an address designation means, 2(2(1) to 2(n), 2(E
ND)) is a storage means that is set by the operation of the address specifying means 1, and 3 is an encoding means with priority, which has a plurality of input terminals, and each input terminal is connected to an output terminal of the storage means 2. has been done.

4 is a position signal reproducing means including a magnetic head and an amplification/detection means; 5 is a position signal reproducing means 4 that counts the position signals reproduced by the position signal reproducing means 4 and generates outputs B, C, and D at the first to third output terminals, respectively; Comparing means 7 which receives the output B of the counting means 5 and the output A of the encoding means 3 and outputs their comparison outputs A=B, A<B and A>B to each output terminal;
is a control signal generating means which receives the output of the comparing means 6, the outputs B, C, and D of the counting means, and the output A of the encoding means 3, and generates a control signal for the tape running state. PLA the tape running state in ~11
Generates signals to control the Y state, REW state, FF state and PPAUSE state.

Next, the operation of the magnetic recording/reproducing apparatus having the above configuration will be explained.

First, when the address specifying means 1 corresponding to the address desired for reproduction is operated, the storage means 2 corresponding to the operated address specifying means 1 is set.

The set output of the storage means 2 is applied to the encoding means 3 to generate an output A converted into an address number.

On the other hand, a search command operation causes a control signal to be generated at the output terminal 10, for example, to control the tape to the FF state.

When the position signal arrives, the position signal is reproduced by the position signal reproducing means 4, and the counting means 5 outputs B, C and D.
is generated at each output terminal.

The output B of the counting means 5 and the output A of the encoding means 3 are compared by the comparing means 6. A tape running control signal is generated by the control signal generating means 7 at each output terminal 8-11.

Thus, the running state of the tape can be automatically controlled based on the specified number of addresses and the position signal obtained by counting the playback.

FIG. 2 shows an embodiment of the counting means 5 of the magnetic recording and reproducing apparatus according to the present invention, in which 12 is a counter to which the output of the position signal reproducing means 4 is inputted and outputted in BCD code to each output terminal; -16 are preset terminals.

51 to 54 are interlocking switches, the common contacts of which are connected to the preset terminals 13 to 16, and the non-common contacts of K in the first state (solid line) of the interlocking switches 51 to 54.
The complement of is preset, and in the second state (dashed line) (K+1
Ground or H so that the two's complement of 0) is preset.
It is connected to the IGH level terminal 55.

FIG. 2 shows the connection when K=2.

17 receives the most significant bit output of the counter 12, and when the input changes from "H" to "L" level, output terminal 18
Flip-flop circuit that generates “L” level at 19
20 is a latch circuit in which the output terminal 18 of the flip-flop circuit 17 is connected to the input terminal and the most significant bit output terminal of the counter 12 is connected to the clock terminal; 20 is the latch circuit 1;
This is the output terminal of 9.

Next, the operation of the counting means 5 having the above configuration will be explained.

For convenience of explanation, it is assumed that the number of bits of the counter is 4 and the maximum number of addresses that can be specified is 15.

Let the number of pulses of the position signal corresponding to addresses 1 to n and END be (K+1) to (K+n) and (K).

First, the operation when the preset of the counter 12 is changed by the interlocking switches 51 to 54 will be described.

When the interlocking switches 51 to 54 are in the first state (solid line), the output B of the counter 12 becomes 0 with K input pulses, and (
K+1) (K+n) (K≦15), which is 1 to n.

On the other hand, when the interlocking switches 51 to 54 are in the second state (broken line), the output B of the counter 12 becomes 0 with (K+10) input pulses (K+10+1) to (K+10+n).
(n≦15) and becomes 1 to n.

Therefore, the correspondence between the stored address by the address designation operation and the position signal reproduced and counted changes relatively, and it is possible to accurately designate more addresses than the number of address designation means by the preset difference.

Is the next arriving signal an invalid pulse less than K? 1 to 15
The operation of determining whether the pulse corresponds to the address specifying means of number 1 or the pulse corresponding to address 16 or more will be explained.

First, the case where the interlocking switches 51 to 54 are in the first state will be described.

In this case, the output B is 1 to n in response to pulses (K+1) to (K+n), and the output B is 0 with K pulses.
becomes.

On the other hand, outputs C and D are "H" and "H", respectively, for pulses below (K-1), and "L" and "H", respectively, for pulses of (K to K+15) f, (K+16). For the above pulses, the level becomes "L" and "L", respectively.

For example, for pulses (K+3) and (K+16+3), output B is 3, but outputs C and D are 3.
It is possible to recognize a signal corresponding to an address and a signal corresponding to an address of 16 or more, and to recognize a pulse less than K as an invalid pulse.

Next, the operation when the interlocking switches 51 to 54 are in the second state will be explained.

In this case, (K+10+1) ~ (K+10+n) (n
In response to a pulse of ≦15), the output B becomes 1 to n, and (
The output B becomes O with a pulse of K+10).

On the other hand, outputs C and D are "H" and "H" respectively for pulses below (K+10-1), and (K+10) to (K+
10+15) pulses are “L” and “H” respectively.
, (K+10+16) or more pulses become "L" and "L", respectively.

For example, for the pulses of (K+10+3) and (K+10+16+3), output B is both 3, but outputs C and D identify them as pulses corresponding to addresses 13 and 26 or above, and pulses below (K+10-1) can be recognized as an invalid pulse.

FIG. 3 shows an embodiment of the control signal generating means 7 of the magnetic recording and reproducing apparatus according to the present invention, where 21 is an AND gate into which the outputs C and D of the counting means 5 are input, and 22 is the output of the counting means 5. 24 is a NOR gate to which the outputs C and D of the counting means 5 are input; 25 is the NOR gate to which the output B of the counting means 5 is input; A gate circuit whose output becomes "H" when there are K pulses, that is, when output B is 0; 26 is an OR gate to which the outputs of the NOR gate 24 and the gate circuit 25 are input; 27 is the output A of the encoding means 3; is input and the input is END(1(E
ND)), a gate circuit whose output becomes "H"; 28 is the output of the OR gate 26 and the inverter 2;
NAND to which the output of gate circuit 2T is input via 9
30 is a NAND gate to which the outputs of the OR gate 26 and gate circuit 27 are input; 31 is an OR gate to which the outputs of the NAND gate 22 and gate circuit 27 are input; 32 is the output of the NAND gate 28 via an inverter 33; and the output of the OR gate 31 and the output of the NAND gate 30 via the inverter 34 and the A=B of the comparison means 6.
OR gate to which the output terminal is connected, 35 is inverter 3
The output of the NAND gate 30, the output of the OR gate 31, and the A<B output terminal of the comparing means 6 are connected via 34, and the output terminal of the NAND gate 28 is connected via the inverter 33. and an OR gate 37 to which the output of the NAND gate 30 and the A>B output terminal of the comparing means 6 are connected via the inverter 34.
are NAND gate 28 and OR gate, 37 is NAND
AN to which the outputs of the gate 28 and the OR gate 35 are input.
D gate, 38 is gate circuit 25 and NAND gate 2
39 is a NAND gate to which the outputs of gate circuit 27 and NOR gate 38 are input.
Gate 40 is OR gate 36 and NAND gate 39
41 is a NOR gate to which the outputs of the NAND gate 22 and gate circuit 27 are input; 42 is a NAND gate 30 and a NOR gate 41;
43 is AND gate 2
1 and an OR gate into which the outputs of the OR gate 32 are input;
44 is an OR gate into which the outputs of AND gate 21 and AND gate 37 are input; 45 is AND gate 21 and A
46 is an OR gate to which the output of AND gate 21 and OR gate 42 is input; 47 to 50 are flip-flop circuits; The output terminal of is connected, and the reset terminal is OR
The output terminals of the gates 44 to 46 are connected, the output terminal of the OR gate 44 is connected to the set terminal of the flip-flop circuit 48, and the OR gates 43 and 45 are connected to the reset terminal.
The output terminals of the OR gates 45 and 46 are connected to the set terminal of the flip-flop circuit 49, and the output terminal of the OR gate 45 is connected to the reset terminal of the flip-flop circuit 49.
The set terminal of the flip-flop circuit 50 is connected to the output terminal of the OR gate 46, and the reset terminal is connected to the output terminals of the OR gates 43-45.

Next, the operation of the control signal generating means 7 having the above configuration will be explained.

It is assumed that the counter is in the first preset state.

First, a case where the number of position signals is (K-1) or less will be explained.

At this time, the outputs C and D of the counting means 5 are both “H”
level, and the output of the AND gate 21 becomes "H".

Since this output is input to each input terminal of the OR gates 43-46, no change is made to the flip-flop circuits 47-50 no matter what the output of the comparing means 6 or the like is.

Next, a case where the position signal is (K+1) to (K+15) and the output of the encoding means 3 is other than END will be explained.

At this time, the output C of the counting means 5 is "L" and the output D is "
"H", the output of the NAND gate 22 becomes "L", the output of the gate circuit 27 becomes "L", and the output of the OR gate 31 becomes "L".
The output of the NOR gate 24 and the gate circuit 25 are also "L", and the output of the OR gate 26 is also "L".
The output of the NAND gate 28 becomes "H", the output of the inverter 33 becomes "L", the output of the gate circuit 27 also becomes "L", and the output of the NAND gate 30 becomes "H".
Therefore, the output of the inverter 34 becomes "L", and the NAND
The output of the gate 39 becomes "H" and the output of the AND gate 21 becomes "L".

Therefore, the output of the comparing means 6 is directly OR gates 43 to 4.
5, and its output causes flip-flop circuit 4.
7 to 49 are controlled.

Therefore, A=B output of the counting means 6, A<B output and A>
When each of the B outputs becomes "L", the flip-flop circuits 47 to 49 are set, and the output terminals 8 to 10 are set.
When each becomes "H", the tape running becomes PL.
Controlled to Y state, REW state and FF state.

At this time, the output of the NOR gate 41 becomes "H",
The output of the OR gate 42 becomes "H", and the OR gate 42
Since the output of the OR gate 46 is "H" and the output of the OR gate 46 is also "H", the flip-flop circuit 50 is not set.

Next, a case where the position signal is (K+1) to (K+15) and the output of the encoding means 3 is END will be explained.

At this time, the output of the gate circuit 27 is "H" and the OR
The output of gate 31 becomes “H” and OR gates 32 and 35
and 36 outputs are all "H".

The output of the NAND gate 28 is still "H", and the output of the AND gate 37 is "H", so the OR gates 43 and 44
The output cannot be "L".

Further, the output of the OR gate 26 is "L", so the output of the NAND gate 30 is "H", the output of the OR gate 42 is "H", and the output of the OR gate 46 cannot be "L" either.

On the other hand, the output of the gate circuit 25 becomes "L" and the output of the NOR gate 38 becomes "H".

Therefore, the output of the NAND gate 39 becomes "L", and the AN
The output of the D gate 40 becomes "L".

Since the output of AND gate 21 is also "L", the output of OR gate 45 is also "L", and flip-flop 49 is set.

Therefore, the output terminal 10 becomes "H" and the tape running is controlled to the FF state.

That is, the FF state is entered to search for the END recorded at the end of the final address.

Next, the case where the position signal is K or (K+16) or more and the output of the encoding means 3 is other than END will be explained.

At this time, the output of the NOR gate 24 becomes "H",
The output of the N4ND gate 28 becomes "L".

Therefore, the output of the inverter 33 becomes "H", and the outputs of the OR gates 32 and 36 cannot become "L".

The output of the gate circuit 27 is “L” and the NAND gate 3
The output of 9 is "H".

Therefore, the output of AND gate 40 is also "H".

The output of the NAND gate 30 is still "H", the output of the OR gate 42 is "H", and the output of the OR gate 46 is also "H".
H”.

On the other hand, since the output of the NAND gate 28 is "L", AA
The output of the ND gate 37 becomes “L”, and the output of the AND gate 2
Since the output of the OR gate 44 is also “L”, the output of the OR gate 44 is “L”.
The flip-flop 48 is set and the output terminal 9 becomes "H", and the tape running is controlled to the REW state.

That is, when the address specification is 1 to n, when a position signal corresponding to the maximum address that can be specified or more arrives, the program is rewound and controlled to search for a younger address.

Next, the case where the position signal is K or (K+16) or more and the output of the encoding means 3 corresponds to END will be explained.

At this time, the outputs of the NOR gate 26 and gate circuit 27 are both "H", and the output of the NAND gate 30 is "L".
”, and the OR gates 32 and 3 are connected via the inverter 34.
The inputs of 5 and 36 are set to "H".

In addition, the output of the NAND gate 28 becomes “H” and the
The output of the gate 37 also becomes "H".

Further, one of the inputs of the NOR gate 38 becomes "H" and its output becomes "L", causing the output of the NAND gate 39 to become "H".

Therefore, the outputs of OR gates 43-45 are all "H".

On the other hand, the outputs of the NAND gate 30 and the NOR gate 41 are both "L", the output of the OR gate 42 is "L", and the output of the AND gate 21 is also "L", so the OR
The output of the gate 46 becomes "L", and the flip-flop 5
0 is set, the output terminal 11 becomes "H", and the tape running is controlled to the PAUSE state.

That is, when the specified address is END and a position signal corresponding to END or the maximum address that can be specified arrives, the tape running becomes a PAUSE state, and it is possible to easily locate and reproduce information at the maximum address that can be specified.

As described above, according to the present invention, by using (K+1) to (K+n) pulses as the position signals corresponding to addresses 1 to n and K pulses as the END signal, desired information can be obtained by address designation operation. In addition to automatically selectively reproducing pulses, pulses less than K are recognized as invalid pulses, and pulses of (K+n+1) or more are controlled in the same way as for K pulses, that is, addresses 1 to n. If END is specified, it is controlled to the REW state; if END is specified, it is controlled to the PAUSE state; when END is specified and a pulse of (K+1 to K+n) arrives, it is controlled to the FF state; 1 to n for infinite pulses and addresses
It is possible to provide a magnetic recording and reproducing device that can automatically select and reproduce address information, and extremely easily cue and reproduce information of addresses that are greater than the maximum address that can be specified plus one.

As described above, according to the present invention, as a position signal indicating an absolute address, (K+i) pulses are used for the i address, and K pulses indicating the END of the program are used at the end of the final information. is reproduced and counted, the address is memorized by the address designation operation corresponding to the address desired to be reproduced, and by comparing and outputting the stored address and the position signal which has been reproduced and counted, pulses of (K-1) or less are treated as invalid pulses. For pulses corresponding to (maximum specifiable address + 1) or more, a control signal similar to the above K END pulse arrival is obtained, and
It is possible to provide a magnetic recording and reproducing device that relatively increases the designated address by switching the preset of a counter that counts position signals.

Furthermore, 1 to n and END are provided as address designation means,
It is possible to provide a magnetic recording and reproducing device that sets the lowest search priority to END, controls the PAUSE state when END is specified, and easily searches and reproduces information at addresses (n+1) and above.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the magnetic recording/reproducing apparatus according to the present invention, FIG. 2 is a diagram showing an embodiment of the counting means of the magnetic recording/reproducing apparatus according to the present invention, and FIG. 3 is a block diagram showing an embodiment of the magnetic recording/reproducing apparatus according to the present invention. FIG. 3 is a diagram showing an embodiment of a control signal generating means of the recording/reproducing apparatus. 1 (1 (1) ~ 1 (n), 1 (END))...
Address designation means, 2(1) to 2(n), 2(END))・
... Storage means, 3... Encoding means,
4... Position signal reproducing means, 5... Counting means, 6... Comparing means, 7... Control signal generating means.

Claims (1)

[Scope of Claims] 1. As an address signal for distinguishing the position of the magnetic tape, (i) an address (K+i
) (K is a positive integer) pulses are recorded at the end of the final address, and K pulses indicating the END of the information are recorded, and the address of the information desired to be reproduced is memorized by the address designation operation at the time of retrieval, and the address of the information desired to be reproduced is stored at the memory address. A control signal for the tape running state is obtained by a comparison output between the position signal and the position signal obtained by counting the playback, and the desired information is selectively played back. 1 preset state, pulses less than (K-1) are recognized as invalid pulses, and position signals corresponding to addresses greater than or equal to [maximum specifiable address + 1] are treated in the same way as the arrival of K pulses above. 1. A magnetic recording/reproducing device which obtains a control signal and increases the number of designated town addresses by relatively changing the correspondence between a storage address and a position signal counted for reproduction in a second preset state. 2. The address specifying means includes 1 to n and END, the lowest search priority is END, and when END is searched, the tape running state is controlled to PAUSE state. Magnetic recording and reproducing device.