JPS58155456A - information processing equipment - Google Patents

Abstract

PURPOSE:To obtain the quotient and residue as a result of operation with high accuracy, by controlling the number of times of repetition so that the quotient of a division of a numerical value expressed by a floating point format is obtained as an integer value, and constituting so that the quotient of an integer and the residue in that case are obtained. CONSTITUTION:A register 7 holds a sifference between a value of an exponential part register 1 of a dividend and a value of an exponential part register 3 of a divisor, and decides the number of times of repetition of a division. The division is executed by 3 processings consisting of pre-processing, repeated processing and post-processing. In the pre-processing, an initial condition for the division which does not execute add-return is set. Subsequently, in the repeated processing, the division which does not execute add-return is executed, and the operation is executed to 0.5 or -0.5 as the quotient. Subsequently, in the post- processing, the operation for correcting the value whose last quotient of repetition is 0.5 or -0.5, to an integer is executed. In this way, the quotient of a division of a numerical value expressed by a floating point format is obtained as an integer value, by which the quotient of an integer and the residue in that case can be obtained exactly.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device that provides a quotient and a remainder of a division of a floating point number onto a general-purpose register or the like based on an arithmetic instruction of an electronic computer.

In this type of information processing apparatus, arithmetic operations on a uniform number are usually performed using floating point numbers. In conventional floating-point division, a quotient is obtained by dividing up to the required degree, and no remainder is obtained. However, there are cases where the entire remainder is required when the quotient is calculated until it is obtained as an integer value.

In order to obtain this, conventionally, for example, (U.S. Patent No. 3
, 871, 578) can be used. In such a conventional device, multiplication is performed using the reciprocal of a number that should originally be a divisor as a multiplier, and the integer part and decimal part are completely separated and each is used as an operation result. However, since this calculation is essentially an approximation method, it cannot be used for calculations that require an exact remainder.

That is, conventionally, multiplication is performed using the reciprocal of the divisor as a multiplier, so even if the divisor is generally correctly represented as a floating point number, the floating point representation of the reciprocal cannot be used as a correct value. This is the first reason why it is an approximate calculation. Next, the integer part above the decimal point of the product value with the reciprocal of the divisor represents the correct quotient, but the small a part below the decimal point of the product value &'X% does not represent the remainder up to this t. , the product of this value and the divisor is the remainder. The second reason why this calculation is an approximation is that an error occurs when calculating the remainder.
I'll go. Conventionally, due to one or more of two reasons, only approximate calculations were performed and it was not possible to obtain an accurate remainder.

SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing device that can obtain a quotient and a remainder as a result of a calculation very well in the division of floating point data.

#! 1 and 2nd registers, 3rd and 4th registers that hold the exponent part and mantissa part of the divisor, respectively;
a computation means, a comparison means for determining whether the signs of the second and fourth registers are the same, and addition or subtraction of the contents of the second and fourth registers according to the comparison result of the comparison means. The calculation by the second calculation means is repeated nine times according to the calculation result by the first calculation means, and in the intermediate process, the mantissa part of the divisor is calculated by the second calculation means. The present invention is characterized in that it includes a control means that updates the result and moves the value of the mantissa part of the divisor by digits.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. ys1 shows the configuration of an embodiment of the main part of the information processing device according to the present invention.

In FIG. 1, registers 1 and 2 are registers that hold the dividend at, and consist of an exponent register 1 and a mantissa register 2. Register 3.4 is a register that holds the divisor, and consists of exponent register 3 and mantissa register 4. register 5
．． Reference numeral 6 denotes a register for holding the entire remainder of the operation result, which is comprised of the exponent part register 5 and the mantissa part register 6. It is assumed that the data held in these three registers is in normalized floating point representation. If the data has not been normalized, it is conventional to perform normalization processing prior to the processing described below. Furthermore, when the value of the divisor is 0, it is treated as an exception to conventional division. When the value of the divisor is not 0 and the value of the dividend is 00, the remainder and quotient are set to 0. The following explanation will be given for the case where both the divisor and the dividend are not 0.

Although there are various expression formats for the exponent part and the mantissa part, the following will be used here for convenience of explanation. It goes without saying that there is no essential difference and the invention is applicable even if other forms of expression are used. That is, the exponent part is narrowed to an integer, and its negative number is expressed as a two's complement number. The mantissa part is represented by a binary bit string of a numerical value that satisfies the following inequality regarding the value X, and its negative number is represented by a two's complement number.

-2≦x〈-1 times 1≦x (2 register 9 is a register that holds intermediate remainder during division,
The leftmost bit 10 represents the sign of the remainder. code 1
It is customary that when 0 is the value O, it is non-negative, and when the value 1 is negative, it is negative.

Register 9 first stores the value of the mantissa of the dividend, which becomes the first intermediate remainder. Register 11 is a register for storing the value of the mantissa of the divisor, and its value does not change during division. Note that the register 9 can also be used as the register 2, and the register 11 can also be used as the register 4.

Register 7 is a register that holds the direct difference between the value of dividend exponent register 1 and the value of divisor exponent register 3, and is used to determine the number of repetitions that constitute the main part of division. Register 8 is a shift register, and the value is set according to the result of sign comparator 15, but the setting method is 3 steps of division (phrase preprocessing, (b) repetition, (C)
Depends on post-processing. The arithmetic unit 14 performs addition and subtraction, and the result of the comparator 15 determines whether addition or subtraction is performed. This arithmetic unit 14 is.

When the result of the comparator 15 is 0, that is, the sign of the intermediate remainder and the sign of the divisor do not match, the adder
It works as a subtractor when both codes match. The arithmetic unit 13 always works as a subtracter, and holds the result of subtracting the value of the input 13b from the register 3 from the value η of the input 13a from the register in the output register 7.

Note that the arithmetic unit 14 may also serve as the arithmetic unit 13.

The result is determined by the values of the sign bit 1o of the register 9 and the sign bit 12 of the register 1 in the comparator 15tl.As shown in FIG. 2, the result is 11 when the two forces are equal and 0 when they are not equal.

Tashif $16 converts the value of register 9 into the first human power 1 of arithmetic unit 14.
This is a sophisticated method that transfers the data shifted by 1 bit to the left in 4m. In addition to the bus bar 20 that is shifted to the left by one bit, a bus bar 21 that is not shifted is provided.

#I3 shows an example of a controller Jld that performs division by the device shown in FIG. 1, and these controls are performed by a processor not shown.

Division consists of three processes: (a) preprocessing, (b) iterative processing, and (C) postprocessing, and these will be explained in sequence with reference to FIG.

First, the value of the mantissa register 2 of the dividend is transferred to register 9, and the value of the mantissa register 4 of the divisor is transferred to register 11 (
Steps 31 and 32 in FIG. 3) Transfer the value of the register 9 through the bus 21 as the first human power 14a of the reenactor 14. Also, the value of the register 11 is input to the second manual input 1 of the arithmetic unit 14.
Transfer as 4b. The result of subtraction by the arithmetic unit 14 is transferred to the register 9. On the other hand, the sign bit 10 of register 9 and the sign bit 12 of register 11 are sent to comparator 15 for comparison, and if both bits are the same, 1 is output, and if not, 01 is output. The value of the comparison result of the comparator 15 is
When the value is 0, all the shift registers 8 are set to 1, and when the value is 1, all the values are set to 0 (step 33 in FIG. 3). this is,"
This is the setting of the initial conditions for an operation known as "division without addition." Normally, this operation is realized by performing the same operation as the iterative process in the next section and finally inverting the sign bit between 0 and 1. However, in the case of the present invention, unlike the general method, the number of iterative processes in the next section is is different from the effective number of bits in the mantissa.

This is because it cannot be realized only by inverting the last sign bit between 0 and 1.

The value of the exponent part register is entered as the first manual input 13a of the arithmetic unit i3, and the value of the exponent part register 3 is input to the arithmetic unit 1.
Insert it as the second human power 13b of 3.

The calculator 13 calculates the value of the second human power 13 from the value of the first human power 13a.
The value of b is subtracted and the resulting value n is held in the register 7 (step 34 in FIG. 3). (b) Iterative processing The following is performed as many times as the value n in the register 7 plus 1.

That is, the value n of register 7 is checked (step 35 in FIG. 3), and if it is not negative, it is decreased by the value 'kl of register 7 (step 36 in FIG. 3), and the comparator 15 The codes of 9 and 11 are compared (step 37 in FIG. 3).

The value of the register 9 is transferred to the first input 14a of the arithmetic unit 14 via the shifter 416 and the bus 20. The value of register 1 is transferred as second manual input 14b of computing unit 14. Depending on the result of the comparator 15, the arithmetic unit 14ffi is operated as an adder or a subtracter, and the output result is transferred to the register 9 (steps 39 and 41 in FIG. 3).

Also, the contents of the shift register 8 are shifted to the left by one bit, making it the rightmost bit, and the value of the result of the comparator 15 is set (step 38.40 in FIG. 3).

This part of the processing is an operation known as "division without adding back." When the remainder and the divisor have the same sign, the quotient 1 is set and subtracted; when the remainder and the divisor are different signs, the quotient -1 is set and added. According to this operation, the bit of the latest quotient is always 1, but the previous quotient remains 1 when the quotient l stands, and the bit of the quotient - 1
When it stands, it becomes 0 due to the debt of subtraction. therefore,
As the previous quotient, if the signs are the same, 1. When the signs are different, 0 is excited.

From the above, we must consider that when we finish this iteration, the final quotient is l.

The reason why the number of repetitions is determined by adding 1 to the value of register 7 is to obtain the quotient up to 0.5 or -0.5. As a result, the range of the remainder r becomes the next range depending on the divisor d.

-Idl/2<r<ldl/2 By setting the range of the sting margin r as described above, the primary post-processing can be facilitated.

(C) The value of the post-processing register 9 is passed through the entire bus line 21 to the first
Transfer as 14M manpower. The second manpower remains the same as before. In the arithmetic unit 14, a comparator 15
Performs all additions or subtractions depending on the comparison result, and transfers the operation result to register 6 (step 43 in Figure 5).
. The value subtracted from the value in register 3 is transferred to all registers 5.

Regarding the shift register 8, when the value of the comparator 15 is O, it is left as is, and when it is 1, it is incremented by 1 (step 42 in FIG. 3).

This process is performed as follows: (the last quotient of the cut repetition is 0.5 or -
This is for correcting 0 and 5 to integers.

In decimal point format, the remainder in registers 5 and 6 is obtained in floating point format. Transformation from fixed-point format to floating-point format and normalization of floating-point numbers may be performed as necessary.

According to the invention, iterative times to obtain the quotient of division of numbers expressed in floating point format as an integer value! By controlling I2 and providing the means to obtain the quotient of an integer and the remainder at that time, it is possible to obtain the remainder correctly.1 For example, calculations such as periodic function values described below can be performed with great accuracy. .

Let's look at an example that shows the effect of being able to calculate the quotient and remainder at the same time in division of floating-point numbers.

Trigonometric functions are periodic functions. Among these, the period of the tangent function is π (pi) when expressed by the arc degree method.

However, the following relational expression is also known.

tan((2i+1)K/2+r)=-1/1
anrUsing this, the value of the tangent function can be calculated based on the calculation of the value of tan r when π/4<r<π/4, so the period is essentially 2/2. I can't help but think about it. Furthermore, many subroutines for calculating tangent functions have conventionally been created in this manner.

From the above, the tangent function value can be calculated in the following two steps by dividing the independent variable X by /2 and finding the quotient q and the remainder r.

(a) Find the value of taor using the tangent function value calculation routine in the interval -/4<r<π/4.

(b) Depending on whether Q is even or odd, when q is an even number, when it is an odd number, 1/1 anri is calculated.

Here, q is an integer, and r is determined to satisfy the following interval.

K/4 (r (ni/4) In this way, there are cases where it is effective to calculate not only the remainder but also the quotient at the same time, and this is often the case when calculating trigonometric functions.

Theoretically, the range of values that can be obtained as a remainder cannot be determined exactly, but in practice it is best to choose one of them that has the smallest absolute value. . The reason for this is that floating point representation is used to preserve the number of significant digits of a number as much as possible, so for numbers with small absolute values, the fineness of the absolute value is preserved. be. Therefore, the possible range of the remainder value r is the absolute value of the divisor ((when d).

−d/2<r<d/2. The symbols are not limited to those above,
It may be attached to the inequality sign on the right, or it may be determined by the signs of the divisor and dividend, and there is no practical problem.

Conventional devices (for example,
Compared to U.S. Pat. No. 3,871,578), the present invention has the following effects.

(1) In the conventional method, the quotient in floating-point division is 91 in total.
- It can be calculated, but the remainder cannot be directly calculated, and it is rare and has not yet been invented.

Along with the quotient, the remainder can be calculated directly.

(2) In the conventional method, a remainder can be obtained by multiplying the decimal part obtained by 1 by a divisor d, but this is not a correct value, whereas the present invention can obtain a correct remainder.

(3) In the conventional case, the result of multiplication of floating point numbers is
Although it obtains the same number of significant digits as the multiplier, the number of significant digits in the decimal part decreases by the number of significant digits in the integer part above the decimal point, so it cannot be used as an alternative to the remainder calculation. The present invention does not have such disadvantages.

(4) In conventional methods, approximation formulas such as trigonometric functions are simple functions of the independent variable, but when using the decimal part by multiplication, the independent variable is a single function. Since we have to use a formula that has been converted to
While these errors combine to create a large error,
In the present invention, such errors do not occur at all.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the main parts of an information processing apparatus according to the present invention, and FIG. 2 is a flowchart showing an example of the comparator of FIG. 1. 1 to 12...Register, 13.14...Arithmetic unit, 1
5Yi+ Inferior 3 figure

Claims (1)

[Claims] 1, first and second registers that hold the dividend to exponent part and mantissa part, respectively; third and fourth registers that hold the exponent part and mantissa part of the divisor, respectively; a first calculation means for calculating the difference between the exponent parts of the registers; a comparison means for determining whether the signs of the second and fourth registers are the same; #! A second arithmetic means for adding or subtracting the contents of the register No. 4 repeats the arithmetic operation by the second arithmetic means a number of times according to the arithmetic result of the first arithmetic means, and in the intermediate process. updating the mantissa part of the divisor with the calculation result of the second calculation means, and
An information processing apparatus comprising: a control means for shifting the value of the mantissa part of the divisor by digits.