JPS58155694U - Tape recorder control circuit - Google Patents

Tape recorder control circuit

Info

Publication number
JPS58155694U
JPS58155694U JP5140282U JP5140282U JPS58155694U JP S58155694 U JPS58155694 U JP S58155694U JP 5140282 U JP5140282 U JP 5140282U JP 5140282 U JP5140282 U JP 5140282U JP S58155694 U JPS58155694 U JP S58155694U
Authority
JP
Japan
Prior art keywords
control circuit
tape recorder
recorder control
counter
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5140282U
Other languages
Japanese (ja)
Inventor
博之 岩佐
Original Assignee
セイコーインスツルメンツ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by セイコーインスツルメンツ株式会社 filed Critical セイコーインスツルメンツ株式会社
Priority to JP5140282U priority Critical patent/JPS58155694U/en
Publication of JPS58155694U publication Critical patent/JPS58155694U/en
Pending legal-status Critical Current

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  • Management Or Editing Of Information On Record Carriers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の実施例を示す回路図、第2図a、  
bは操作方法示す説明図である。 1・・・カウンタ、2・・・メモリ、3・・・Avto
Stop 5w4−−−Load SW、 5−−−E
x−NOR,5−−−ANDゲート、7−ORゲート、
fJ−3t、op SW、9 ・・・制御用IC。 10−RECSW、 11−FF Sw、12−REW
 Sw。
Figure 1 is a circuit diagram showing an embodiment of the present invention, Figure 2a,
b is an explanatory diagram showing the operating method. 1...Counter, 2...Memory, 3...Avto
Stop 5w4---Load SW, 5---E
x-NOR, 5--AND gate, 7-OR gate,
fJ-3t, op SW, 9...Control IC. 10-RECSW, 11-FF Sw, 12-REW
Sw.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] テープ位置を検出するカウンタと、該カウンタの出力を
記憶するためのメモリと、前記カウンタとメモリの出力
の一致、不一致を検出するEx−NOR回路と、該Er
−NoR回路の出力により録音状態を停止状態に変換す
る制御用ICとを有し、録音終了位置を任意に設定でき
る構成としたことを特徴とするテープレコーダ制御回路
。
a counter for detecting the tape position; a memory for storing the output of the counter; an Ex-NOR circuit for detecting coincidence or mismatch between the outputs of the counter and the memory;
- A tape recorder control circuit characterized in that it has a control IC that converts a recording state into a stop state by the output of a NoR circuit, and is configured to be able to arbitrarily set a recording end position.
JP5140282U 1982-04-09 1982-04-09 Tape recorder control circuit Pending JPS58155694U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5140282U JPS58155694U (en) 1982-04-09 1982-04-09 Tape recorder control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5140282U JPS58155694U (en) 1982-04-09 1982-04-09 Tape recorder control circuit

Publications (1)

Publication Number Publication Date
JPS58155694U true JPS58155694U (en) 1983-10-18

Family

ID=30062117

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5140282U Pending JPS58155694U (en) 1982-04-09 1982-04-09 Tape recorder control circuit

Country Status (1)

Country Link
JP (1) JPS58155694U (en)

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