JPS5816355A - Fault detecting system - Google Patents

Abstract

PURPOSE:To facilitate an easy detection for a device suspicious of a fault in a program loading system of a data processor, by discontinuing the execution of a program at a moment a fault arises and limiting the range of fault for the data processor. CONSTITUTION:A program is loaded to an intenal storage device 4 from an external storage device 5, and then a proper pattern applied previously to the program is checked. The program is started when the pattern is identical with a prescribed one. While a fault is deteted if the pattern is not normal. Thus the progress of the program is discontinued at a moment a data processor has a fault. This shorten the recovering time of the faulty data processor and at the same time limits the range of fault. In such way, a device suspicious of a fault can be easily detected.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a fault detection method for stopping the execution of a program when a fault occurs in a data processing device or the like.

Generally, data processing devices employ a program loading method in which programs and data required for processing are read out in advance from an external storage device called a program library to an internal software overlay 177. This guarantees high speed and versatility in data processing.

However, in conventional data processing devices, even if an erroneous program different from the predetermined one is loaded into the overlay area of the internal storage device, it is difficult to know when a failure occurs when such an erroneous program is loaded. It is only when the program is executed that it becomes clear that a failure has occurred.

This causes a problem in that the time required to repair the data processing device is delayed, it becomes difficult to limit the range of the fault, it takes time to discover a suspected faulty device, and it takes a long time to repair the data processing device.

An object of the present invention is to execute the program at the point of failure of the data processing device based on the idea of checking the unique gloss turn given in advance to the program after loading the program from the external storage device to the internal storage device. The purpose is to stop the system and thereby limit the extent of the failure in the data processing unit, thereby facilitating the discovery of faulty documents and suspect devices.

According to the present invention, in the r-processing device, a platform for loading a plurality of programs into an external storage device or an internal storage device and executing instructions constituting each program, and a platform provided in advance for each program. A fault detection method is provided which is characterized in that a unique pattern for checking is checked, and if the pattern is a predetermined pattern, the glogram is operated, and if the noreen is abnormal, it is detected as a fault.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below by way of embodiments and with reference to the drawings.

FIG. 1 is a block diagram showing an apparatus for implementing a failure detection method according to the present invention. The apparatus shown in FIG. 1 consists of an overlay program registration table address designation section 1, a loading circuit 2, and a pattern check section 3. It is configured to check whether

Overlay program registration table address designation Triggered by an N1 overlay calling program, for example, cuLPNi, the contents of the program number storage register 11 are input to the adder 14 along with the contents of the registration table number storage register 12 via the decoder 13. has been done.

The output information of the adder 14 should be loaded! address in the program number registration table, the output information is supplied to the loading circuit 2, and the management table for loading program PT is stored in the internal storage device 4. External storage device address Ii:mi, internal storage device address M
MA1 and the number of transfer words WC1 are provided, and the program corresponding to PNi is loaded.

Further, the output of the loading circuit 2 is supplied to a main turn check section 3.

In the pattern check section 3, a program number storage register 31 is connected to NAND f-) 32 and AND GO) 33, and is connected to terminal B of NAND P-) 32 and AND f-) 33.
A clock pulse is supplied to each of the terminals.

The above Nantes Gate 32 and f-) 33 #'i or P
-) 34, and the OR gate 34 comparison circuit 35
It is connected to the. Also, in the comparison circuit, the above OR f-)3
5, a circuit 44 for calling the program number and its complement PNi, PNi as a fixed/4' turn of the program loaded into the overlay area 43 is connected. Comparison circuit 35Fi Compares and checks the unique pattern of the program to be loaded with the unique pattern of the actually loaded program and program, and if an incorrect program is loaded, it is detected as a failure. If the predetermined program is not executed and a predetermined program is loaded (reference numeral R), the instructions of the reloaded nologogram are executed as shown by the broken line e. In addition, there are 44 pattern recall circuits, two registers 441 and 441', and two AND f-)
442.443 and 1) OR f -) Formed from 444, terminal B is /f turn check section 3's NAND dart 3
2, and the clock pulse is C
From the independent circuit of PU (not shown) #and dart 442
and Nant Gate 32 at the same time. The same applies to terminal A.

Internal storage 4 contains - Overlay calls! program 4
1 is stored, an instruction to start the device shown in FIG. 1,
For example, in the case of CALL PNi, the aviles specifying unit 1 operates first (dashed line a). In addition, the internal storage device 4 stores a management table 42 (address PTA) for overlay grogram loading, and the external storage device 5
The number of the program to be loaded into the overlay area 43 of internal storage [4] is determined by the appropriate group PTA.
pN(1-
E11LIL6 * MMA@ * wco,,-PN
i, Quick Buddha 1. They are registered as Kyobutsu i, WCi, etc. The overlay area 43 is an area where a program is to be loaded from the external storage device 5.

The external storage device 5 contains a unique pattern PN, which is a program to be loaded into the internal storage device 4.

Kyo 7...PNI, Grogram 50 with PNi
．． ...51 is stored.

The apparatus shown in FIG. III above operates as follows.

First, the program i+ to be loaded, for example P
C in the overlay calling program 41 by specifying Ni
ALL PNi is set (dashed line a), register 11 is set to P
Ni is the address P of the registration table in register 1″2.
TA is stored. PNi is decoded by the decoder 13 and supplied to the adder 14, where it is added to the PTA,
The first PNi in group PTAi in internal storage device 4
address is specified (dashed line, b). When this specified address is supplied to the loading circuit 2, the ! in the external storage device 5 corresponding to the Grodarum number PNiK is stored! The program 51 is transferred to the overlay area 43 of the internal storage device 4 (break@a, d).

gate 32 and AND gate 33. If PNi is written as o, o, o, o for each bit in machine language, then PNi ld
l, 1, 1.1. The above-mentioned zologram 51 stored in the external storage device 5 has a unique turn of this PNi and η6.

First, the clock pulse 4' is supplied from the terminal A to open the AND dart 33 and each r-) of the AND gate 443 of the unique pattern calling circuit 44. The above PNi that has passed through the OR gate 34 is supplied to the comparison circuit 35, and the calling circuit 44
register 441 and AND gate 443 and Oγr −)
It is compared with PNi which passed through 444.

If the two are not equal, it is assumed that some fault has occurred and the operation is stopped at that point. If both are equal, the clock pulse is supplied from the terminal i, passed through the NAND P-) 32 and inverted, and the actual overlay area 43
Compare the inverted pattern of the program number PNi loaded in . If the two are not equal, it is assumed that a failure has occurred and the operation is stopped. If the two are equal, the command of the loaded zologram is executed (dashed line @).

According to the present invention, the data processing device It is possible to stop the progress of the zologram at the time of occurrence of a failure, thereby speeding up the recovery time of the data processing device, and making it possible to easily find a suspected failure device by covering the failure range. Although the above explanation deals with programs, failures can also be detected with data using the same procedure.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a device for implementing the fault verification method according to the present invention. 10.・Overlay program registration table address designation section, 2... Loading circuit, 3... Register for storing management table number for 9-turn zologram loading, 13... Decoder, 14... Adder, 31.
・Grogura Onno use zosta, 32... Nando f-)
, 33...and gate, 34...or dirt, 3
5... Comparison circuit, 41... Overlay calling program, 42... Overlay program registration table,
43... Overlay area, 44... Unique! Turn call circuit, 50, 51...Loading program. Patent applicant Fujitsu Ltd. Patent agent Akira Aoki Patent attorney Kazuyuki Nishidate 1) Yukio Patent attorney Akira Yamaguchi

Claims (1)

[Claims] When a data processing device loads a program, etc. from an external storage device to an internal storage device and executes the program, etc., a unique check pattern given in advance to the program, etc. is checked and checked. A fault detection method characterized in that if the gloss turn is a predetermined one, the program or the like is executed, and if the gloss turn is abnormal, it is detected as a fault.