JPS5816560B2 - Memory protection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage protection method, and more particularly to a storage protection method that reduces overhead, is flexible, and is particularly effective in small electronic computers.

Various methods have been proposed for protecting the main memory in small electronic computers, one of which is generally to use a memory protection register.

That is, by providing a memory protection register of, for example, 64 bits, it is possible to protect the main memory in a range of 64 bytes in units of IK bytes.

It goes without saying that the 64th byte is within the range that can be directly specified in the address field of the instruction word.

However, in such a memory protection method, since the unit of memory protection is IK bytes, fine-grained protection is difficult and reliability is poor.

Also, in terms of hardware, even if it is a small computer, 6
Although it is possible to implement more than 6 bytes in 4 bytes, and programs can also use such main memory, protection is limited to 6 bytes.
Since it is fixed at 4 bytes (depending on the capacity of the register), there is little flexibility.

Furthermore, complex bit operations were required to set a write-enabled area within the storage protection register.

The present invention has been made in view of the above-mentioned drawbacks, and the main purpose of the present invention is to obtain a system-optimal storage protection mechanism when the logical address space is expanded. By flexibly relating the memory protection area to the pace register specified by the command word, that is, the software area specified by the instruction word, the number of protection checks can be reduced, and the processing related to memory protection by the operating system can be reduced. A protection area is set according to the program structure of the task to be executed, that is, a variable number of program partitions are prepared in main memory, and a memory protection method is provided in which the task is executed within these partitions. The purpose is to

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 shows the format of an instruction word used in the present invention. In the figure, OP indicates an instruction code section, and R1 indicates a general register number and represents the first operand of the instruction.

XI also indicates the General Registry number, but its contents are used as an index for index modification.

B indicates the pace register number and is used in pace modification of the operand address.

The remaining DISP is a display stand for operand addresses.

Note that ■ is a bit for identifying the format of the instruction word, that is, the short format, and when it is 0'', it is the short format.
1” indicates a long-form instruction word.

FIG. 2 is a conceptual diagram of the hardware used in the present invention. In the figure, 1 is a main memory device MM, which has three program partitions MM, MM2, MM3.

Further, 2 is a main memory protected area setting register MPR;
A pair of registers U and L define one program section.

The two registers indicate the upper and lower limit addresses of the program section, and are indicated by U and L in the figure.

Further, 3 is a main memory protection auxiliary register MBSR, and A in the figure indicates a set of configuration bits of this register, a, b
, c are bits indicating the use of three program sections, and the number of such sets is equal to the number of pace registers.

That is, the main memory protection auxiliary register MBSR3 can indicate to which program section the software area defined by the pace register number specified in the B part of the instruction word applies.

FIG. 3 is a hardware block diagram for implementing the present invention by embodying FIG. 2. In the figure, reference numeral 11 is an instruction word register IR, in which the instruction word currently being executed is set.

The contents set here depend on the format as shown in FIG. 1 above.

Reference numeral 12 is a main memory protected area setting register MPR, in which upper and lower limit addresses of the program partition are set.

Reference numeral 13 denotes a main memory protection auxiliary register MBSR, which consists of bits indicating the use of three program partitions, and consists of, for example, seven bits, the same number as the pace register.

Further, 14 is a memory address register MAR115 that stores the real address of the operand of the execution instruction, and a comparator COMP that compares the main memory protected area setting register MPR12 and the memory address register MAR14.
indicates that the real address is outside the program area and the comparator COMP
The controller CP has a flip-flop for generating an interrupt when a determination is made in step 15, and a counter for checking the three program sections and the real address one section at a time.

Further, 17 is a main memory protection area selection circuit MP R8 which selects one of the main memory protection area setting registers MPR12 under the control from the control unit CP16 and instructions from the main memory protection auxiliary register MBSR13.

The operation of the present invention will be explained in detail below using FIG.

First, the actual address calculation method is not the main purpose of the present invention, so a detailed explanation will be omitted, but it is obtained by adding the display stand specified in the instruction word and the contents of the pace register and index register. It is set in address register MAR'14.

It is checked as follows whether this real address fits within the three program sections.

First, three bits in the main memory protection auxiliary register MBSR13, which are designated by the pace register number indicated in the instruction word register IR11, are selected.

The main memory protection check is performed sequentially on the three program partitions, and the order is specified by a counter in the control unit CP16.

Initially, the contents of the counter 9 are °1'', and the program section N111 is checked, and the main memory protection auxiliary register M
The bit indicated by BSR13 is examined.

When the content of this bit is "0", it means that the main memory protection check is omitted.

When the content of this bit is "1", two registers defining the domain of program partition number 1 in the main memory protected area setting register MPR12, ie, U, Ll, are selected.

Next, the comparator COMP15 checks the validity of the real address stored in the memory address register MAR14 and the content (program section) of the selected main memory protected area setting register MPR12. If it exists outside this program partition, the counter in the control unit CP16 is updated and the validity check is performed in the next program partition.

At this time, the next bit of the main memory protection auxiliary register MBSR13 is checked.

When the content of this bit is 1'', it is checked whether the real address is within program partition %2 as described above.

If such an operation is repeated three times and the real address does not exist in any program partition, a main memory protection violation is detected and a flip-flop in the control unit CP16 is set to generate a main memory protection violation interrupt.

If the real address exists in any program partition, it is determined to be valid, the check is ended at that point, and the instruction is executed.

As explained above, according to the present invention, it is possible to reduce the hardware amount and check time for main memory protection check, and it is possible to variably set an arbitrary number of program partitions in which tasks can be executed on main memory. Therefore, it is sufficiently effective in reducing the overhead of main memory protection management of the operating system and in system maintenance management.

Furthermore, since the partition of each program is determined by the beginning of the partition and the partition size or the end of the partition, fine-grained main memory protection is possible.

[Brief explanation of the drawing]

Figure 1 is the format of the instruction word used in the present invention, Figure 2 is a conceptual diagram of the hardware used in the present invention, and Figure 3 is the hardware for realizing the present invention by embodying Figure 2. It is a wear block diagram. 1... Main memory device MM, 2, 12...
Main memory protected area setting register MPR13, 13...
・・Main memory protection auxiliary register MBSR, 11・・・・
・Instruction word register IR, 14...Memory address register MAR115...Comparator COMP,
16...Control unit CP.

Claims (1)

[Claims] 1. In a computer system having a pace register for belo modification, a first register that defines an arbitrary number of program sections for a storage area and specifies the use of each of the program sections for each pace register; and a second register for setting upper and lower limit addresses of the program section to define the program section, and only when the use of the program section is specified by the output from the first register, the second register A comparison check is performed between the partition defined by the register and the real address generated by the operand address of the instruction regarding memory protection cape.
A storage protection method, wherein use of a storage area is permitted when the real address is within a program partition defined by the second register.