JPS58182196A - Signal transmitting circuit - Google Patents

Abstract

PURPOSE:To eliminate an output signal overlap, by plural stages of circuits which each have a source follower, bootstrap capacitance, and transmission gate, and reducing the circuit scale of shift registers for driving a CCD image pickup element, liquid-crystal display, and memory. CONSTITUTION:An input signal is supplied from an input terminal 1 to a source follower MOST-M21 and a bootstrap capacitor C31 is connected between its GSs. A signal from the M21 is supplied to a following stage M51 through a transmission gate MOST-M41. Similar circuits are connected successively to drive respective stages in out-of-phase states alternately. A transmission gate driven by a signal appearing at the source of a source follower resets the signal of a front stage. Thus, the circuit scale is reduced, the overlap of an output signal is eliminated, and the power consumption is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal transmission circuit suitable for use in a shift register for driving a CCD image sensor, a liquid crystal display, a memory device, etc.

For example, a circuit as shown in FIG. 1 has conventionally been used as a shift register for sequentially driving horizontal scanning lines of a CCD image pickup device line by line.

In the figure, the input terminal (υ is an enhancement type MO
B) Lanzosta T.? -), the source of this transistor T, is connected to the ground line (2), the drain is connected to the source of the MOB) transistor of the deresion lid and the drain of this transistor T is connected to the power supply Line (3) K is connected.

The connection point of the drain and source of this transistor Tl*T constitutes a transformer 2 transistor MOB) A transistor T41-Tst connected in the same way as the transistor Ts-Tm through the source and drain of the transistor Ts. K Ili continuation i! z
tL, the connection point of this transistor 'r411 Tll constitutes a transformer 2 transistor MOB) The same 1 as the transistor Tla TH through the source drain of the transistor T@l! It is connected to Km connected transistors 'ht*T'st...This circuit of transistors Tst-T@1 is connected repeatedly in sequence. Note that the upper part of the f-fix in the figure is shown in common, and the lower part is changed sequentially.

Furthermore, clock signals φ8. φ.

Clock terminals (4) and (5) supplied with the clock terminals (4) and (5) are connected to f-)K of the transistors Tss aTI... and the transistors T@1+TB..., respectively.

In this circuit, at φ, lock signals φ, φ,
is supplied. On the other hand, the input terminal (1) is supplied with a signal φ as shown in FIG. 2C, for example.

As a result, an inverted voltage V□ as shown in the second diagram appears at the connection point □ of the transistor TIIT.

Next, vl is sampled by the signal φ violet and held in the transistor T4.0ff-)■, and a voltage V as shown in FIG. 2E appears. This causes transistor T4
At the connection point (2) of 1#T11, an inverted voltage (3) as shown in FIG. 2 Y appears. For example, the first horizontal scan is driven by this voltage VS.

Further, vs is sampled with the signal -1, and a voltage v4 as shown in FIG. 2G appears at the transistor Tel's ff-) held n1. This allows the transistor T! 1. Voltages V@' + V as shown in Figure 2 H, I, and Jk are applied to the connection point ■ of T1, the gate of transistor T4, and the connection point ■ of transistor T4 and TI3, respectively.
@@Vma appears, and the second horizontal scanning line is driven by this voltage vT. The above-described operations are then performed sequentially.

Here, the condition of V(φ1.φ,) ≧vDD+■th (vDD is the voltage of the power supply line (3)) is satisfied, assuming that the threshold value of the transistor Tg1 r Tgt... that constitutes the transmission dart is vth. In this way, the input signals φ and N are transmitted sequentially, and each horizontal scanning line is sequentially driven.

However, in this circuit, six transistors are required for one stage configuration from transmitting a signal to obtaining the next signal. For this reason, there are problems such as the circuit size is large9, especially when it is integrated into an IC, the chip area becomes large and the cost of the IC increases.In other words, in the above circuit, the transistors T41 m Tll and T? Each signal is inverted at 11T@l, and twice as many elements are required for rounding to obtain in-phase signals.

Furthermore, in the above-described circuit, when a capacitive load is connected to the output side, the waveforms of the output signals shown in FIGS. 2F and 2J become dull as shown by the broken lines. In this case, overlap occurs between adjacent output signals, and for example, when used in an imaging device, the image quality is degraded due to degraded resolution and color mixture.

Furthermore, in the case of the circuit described above, the transistor THaTll
l'rat... is always on, and therefore a through current flows when the transistors Tl*T4t#Tyt... are on, resulting in extremely large power consumption.

Also, since each transistor is driven in the color sum domain,
In particular, large power consumption is required when driving the circuit at high speed.

Furthermore, since different elements of an enhancement type and a desolation type are used, many manufacturing processes are required, for example, when integrated into an IC.

In addition, in the above circuit, the low level of the waveform at the output points ■, ■... is the transistor T41 e Tax s Ta
It is determined by the on-resistance ratio of g + Tll... r! +
r.

However, r is the ON resistance value of the transistor T411T4m... r is the ON resistance value Vll of the transistor I T@1s Tgl... is the voltage of the ground line (2). A residual voltage V' is generated. . Here, in order to reduce the necessary value of v', it is necessary to make r, , rl Obi very hot, but this requires transistors 741 m 74 m...
The chip area of transistor 'rit+T'sx...
When driving a MOS (MOS) lannostar with a force output signal, if there is a residual voltage ``V'' as described above, the threshold value etc. Many restrictions will be added due to the problem of voltage.Furthermore, there is a problem that the signal's dynamic voltage will be reduced by the residual voltage V'.

In view of these points, the present invention has been designed to eliminate the conventional drawbacks with a simple configuration.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 3, an input terminal (1) constitutes a transmission f-) through an enhancement type MOS transistor M1 and an enhancement type MOS transistor M1. of? -) K connected. Is this transistor MtsO? A capacitor C11 for a Pootstrap is connected to the transistor 4t. The source is connected to the dart of an enhancement type MOS transistor Ms through the drain and source of the transistor M41. A Pootstrap capacitor C6 is connected between the sources of the transistors 4s and 11). Further, the drain of the transistor Mil constitutes a transmission f-). Enhancement type MOS) 2 Nzosta M? 1 f-).

Furthermore, the source of the transistor Mll is the transistor Mf.
The sources of transistors MS, , M, , are connected to the next stage circuit through the drain-source connection of MOS transistor Ml1*, which is an enhancement type MOS transistor.
Connected to M・1 dart. This transistor M@H
The source trains of *Mll are each connected between the source of the two previous transistors MIXe MBB and the ground line (2).

This transistor M,,l M2S 8 Mgl *
Mllm Msl *MIS and capacitor C@1iC
The H circuits are connected repeatedly in sequence.

Further, the clock terminal (4) is connected to the dirt of the transistor M1 and the transistor Ms1. It is connected to the drain of yLs1..., and the clock terminal (5) is connected to the transistor Mu6.
Connected to the drain of Mgm...

In this circuit, clock terminals (4), (5)
% Input terminals (1) K receive signals φ, φ1, CK as shown in FIG. 4, respectively. φ! N is supplied. Here, the signal φ1. φ, high level t Vt N low level wo vL to L, (high level t Vn' of No. 1 φ, ',
- Let the level be vL. In addition, the /9 pulses of the signals φ and φ are as shown in the figure (0), [12)..., (21
), (22)...-, and all the fast values of the MOS transistors are vth.

By this, first v, H≦vIi−vth −・−−−
If (1), the signal φ is the A pulse of the signal φ1 [12]
Transistor M1 is transmitted through transistor Mll.
A voltage v1 as shown in the fourth diagram appears at c-1'g.

Next, the voltage V at the source of the transistor Mll (Fig. 4E) is initially Vt -V -VH' -ML)Vth
−・ ”−(2), so the transistor Mat is turned on and yovL
......(3), and when the signal φ1/gurusu [22] comes, the voltage v1 is raised through the capacitor C11, and becomes 0'' ......(
4)■・”””c, +c,” However, CI is the bootstrap capacitance C8, which is the stray capacitance of the transistor Ms, Or-to, and in this case, Vs-Vth≧vl-・-(5), then v2fegvM ′・・・−(6)
Tonari,) Δsis [22
] is extracted.

Furthermore, when the transistor M41 is turned on in synchronization with the signal φmK, the signal φmK is turned on, and the signal φmK is turned on. −
It is also accumulated in g. And this gate ■ voltage Vs
(Fig. 4 F) is Vs Tomi v, """・(7)
As a result, the transistor I Mal turns on, and the transistor 4sl operates in the same way as the transistor Mal.
In the source ■, 臂SIS [13] is highlighted (Figure 114G).

In the same manner, Transis I Mssg M,,...
Signal φ for No X ■, ■......! , φs (
D + /4 Lus (23”l.

[14]...- is extracted (Fig. 4 1.K...
...).

Therefore, in this circuit, the input signal φ! y are transmitted sequentially, and the transistor Mll #411 MH+ MB・
Pulses [1) are sequentially output to the sources of . For example, horizontal scanning lines can be sequentially driven using this /system.

Furthermore, in FIG. 4, the voltage Vl # VB * VB
The voltage rise V, is the capacitance t Cst
# Due to the Pootstrap effect of C4x..., υ is the voltage drop V of the voltage v3,
is generated by the distribution of charges of (Cm+Ca)vH, and Vl (C1+C1) ” Vm (C
m+C1) +VI CL, where C1 is the capacity of the load.

Here, transfer 1#M@, . . . is the output section ■.

■ This is to reduce the residual voltage due to the capacitive coupling and charge distribution that appear in...For example, at the voltage drop v1 mentioned above, the charge of (Cm + Cm) Vg is ) Since it is reset in synchronization with K,
This eliminates the generation of residual voltage due to K.

Also, the voltage V4 m Vg... The voltage drop V.

is, the change in voltage vl, v, ...... is CB I C
It appeared through L. And this voltage ve is dsis [24]% (25
)...K is reset in synchronization.

Furthermore, the voltages V,, V, ... and v, ev, -.
The residual voltage vD of .

If a capacitive load such as a CCD g-image element or a liquid crystal display is used as the load, c, > c
@ a C, ・・・・・・・・・(6) So,
The above-mentioned V, a VC is approximately zero9, and therefore VD is also approximately zero.

Moreover, the capacitance value C1 of the capacitor 011 a C·l... is from the above-mentioned equations (4) and (5), and the transistor Ml, &[41, lhl m+ ++, which becomes the transfer r-) O pressure resistance -1i
BY Toshi Tatoki, just select from these two equations.

In this way, the input signal φ is transmitted,
According to the present invention, the above-mentioned drawback of the conventional method can be overcome. In other words, in the above-mentioned circuit, the one-stage configuration from transmitting a signal to obtaining the next signal is made up of transistors M, L, etc.
, M2S , M, , there are only 104 capacitor Cs elements. Therefore, the circuit scale is small, and the chip area when integrated into an IC is also reduced.

Also, the output signal is the clock signal φ! , is formed by extracting the Δsis of φbird, so as mentioned above, the tarotsuta signal φ
Overlapping of output signals can be easily eliminated by shortening the A sis of l and φ.

Furthermore, unlike conventional circuits, there is no flow of through current, so power consumption is extremely low.

Since each transistor is driven in the linear region,
High-speed driving can be easily performed without increasing power consumption.

Furthermore, since the output signal is obtained by each of the clock signals -1 and φmaro,
This also reduces power consumption.

In the ninth example, only a few elements are required for the tilt protection lid, and the circuit can be formed in a small size and at low cost.

Furthermore, the residual voltage VD in this circuit is extremely small and becomes approximately zero. Therefore, there are no restrictions such as thresholds, and it is possible to make maximum use of Dyna-ken Tsutarenzo.

In addition, FIG. 2 shows another example of the present invention, in which transistor '1 # M2S e Mtk...?
-) are commonly connected transistors M/a M4(#
Myl'... is provided, and this transistor M/
m M41'w MH'......, connect the source and drain of each to the next transistor M*1 e Mli e
Connect to the source of Mam and the ground line (2).

Therefore, in this circuit, transistor M*'#M41'
6M11'...K Therefore, the above voltage V, ~v
D is reset, and the waveforms of each part become as shown in FIG.

Thus, according to this circuit, 1. *The number of elements in ml+ is l
Although the number of elements increases, the residual voltage can be further reduced to a value that can be ignored.

In the circuit described above, the MOB transistor is constructed as follows. In FIG. 7, an N+ source region (6) and a drain region (to) are formed on a P-type substrate α. and source area (6)
A 0° layer α◆ on the surface of the element between the thorn rain regions (to)
is provided, and a Kr-) electrode (b) is deposited thereon.

Therefore, in such MOB) Tungister, r-
) A capacitor is formed at the part (to) where the electrode (b) and the source region (6) meet, and has a capacitance.
-) When the potential increases, a channel (b) is formed between the source region (to) and the drain region (2), and when the potential is high, a channel (b) is formed between the source region (to) and the drain region (2). A capacitor is also formed between the electrode () and the channel.

Therefore, in the above circuit, the capacitor CSt #(1
1++... as gos transistor Mal *
The relationship 011 quantity between MIl -- r-) and the source or channel can be used. The circuit configuration in that case is as shown in FIG.

Furthermore, MOB) transistors alone do not have enough capacity]
In this case, a capacitor may be provided at 15 in Figure 3. In that case, the capacitor is M as shown in Figure 9.
OB) Lanzosta MH1M・1... f-
) and the source/drain.
If ζO field then Mol) Lanzosta M31゜M-1-・
− can be an enhancement type or a diversion type −
.

[Brief explanation of drawings]

Fig. 1 is a connection diagram of a conventional circuit, Fig. 2 is a waveform diagram for explanation thereof, Stripe S diagram is a connection diagram of an example of the present invention, Fig. 4 is a waveform diagram for explanation thereof, and Fig. 5 is another example connection diagram, No. 6
FIG. 7 is a waveform diagram for explaining the same, FIG. 7 is a configuration diagram of an MO8 transistor, and FIGS. 8 and 9 are connection diagrams of still other examples of the present invention. +1) #'i input terminal, (2) is ground line, (4)
, (5) is the clock terminal MlaM@1 *M41
alms aMtlmlas tMsx・・・・−・
is MOB) transistor, cst # c@t ++
++・ is a capacitor. Same Hide Matsukuma! , I4 Figure 1 Figure 3 Figure 2 Figure 4 K VJI -1 Figure 5 Figure 7 Figure 6 K % Figure 8 - 5゛l

Claims (1)

[Claims] 1. An input signal is supplied to a source follower, a capacitance component for putot strap is provided between the gate and source of this source follower, and the signals from the source follower 1 and others are connected to a first source follower.
is supplied to the next stage through the transformer gate.
The source hopper and the first transmission gate are sequentially connected to each other, and the source hopper and the first transmission gate are alternately driven with different phases to each stage, so that the source hopper and the first transmission gate are driven alternately in different phases. A transmission gate Ii2 is provided which transmits the signal power sequentially to each stage and is driven by a signal obtained from the source of the source follower, and the transmission gate Ii3 resets the signal b1 of the previous stage. Signal transmission circuit. 2. A human input signal is supplied to the source follower, a capacitance component for a putot strap is provided to the gate source of this source follower, and the signal from the source follower is supplied to the next stage through the first transmission gate, and the source follower is supplied to the source follower. and a first transmission gate are sequentially connected, and the north follower and the first transmission gate are driven at different phases alternately for each stage, so that the input signal is transmitted to each stage and K.
A second transmission gate is set, which is driven by a signal transmitted in the 11th order and obtained from the source of the source follower, and this second transmission gate resets the previous stage signal, and also resets the signal of the first stage. A signal transmission circuit is provided with a third transmission gate driven in the same phase as the gate, and the third transmission gate (Ii-j) is reset by the third transmission gate (Ii-j).