JPS58190277A - Drive circuit for switching type dc converter - Google Patents
Drive circuit for switching type dc converterInfo
- Publication number
- JPS58190277A JPS58190277A JP7158682A JP7158682A JPS58190277A JP S58190277 A JPS58190277 A JP S58190277A JP 7158682 A JP7158682 A JP 7158682A JP 7158682 A JP7158682 A JP 7158682A JP S58190277 A JPS58190277 A JP S58190277A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- voltage
- output
- point
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 15
- 238000004804 winding Methods 0.000 claims description 14
- 230000001360 synchronised effect Effects 0.000 claims description 9
- 238000007599 discharging Methods 0.000 claims description 5
- 238000007493 shaping process Methods 0.000 claims description 4
- 230000009191 jumping Effects 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 6
- 238000001514 detection method Methods 0.000 description 5
- 230000000670 limiting effect Effects 0.000 description 4
- 230000005284 excitation Effects 0.000 description 3
- 241000270666 Testudines Species 0.000 description 1
- 230000008033 biological extinction Effects 0.000 description 1
- 230000009172 bursting Effects 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003534 oscillatory effect Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/22—Conversion of DC power input into DC power output with intermediate conversion into AC
- H02M3/24—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
- H02M3/28—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
- H02M3/325—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33507—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
Description
【発明の詳細な説明】
励磁巻線に直流電源から適当な時間幅の繰返し力壱@
VC誘起する跳返り電圧全利用する他励式スイッチラグ
渥直流変換装置において、その動作上安定にする几め上
記出力1m又はそれと−じ波形電圧1酵起する検出巻1
171に現れる跳返9寛圧波形のゼ關りロス点會検出し
、その信号により主スィッチの閉時側を確定し、振動波
形とスイッチ動作の同期を取る方式が従来用いられてい
る。[Detailed description of the invention] A repetitive force of an appropriate time width is applied to the excitation winding from a DC power supply.
In a separately excited switch lug DC converter that utilizes the entire VC-induced rebound voltage, the above output 1m or the same waveform voltage 1 is applied to the detection winding 1 to ensure operational stability.
Conventionally, a method has been used in which the zero loss point of the rebound 9 pressure waveform appearing at 171 is detected, the closed side of the main switch is determined based on the signal, and the vibration waveform and switch operation are synchronized.
本発明はこの種方式の装置に必要なスイッチ駆動用信号
発生回路K11lするものであシ、その目的は市販のタ
イマー用ICなどを使用して極めて容重に回路組立を可
能にすると共に1負荷短絡時の過大電流を別個の電流制
限回路を設けることなしに自動的に規定値以下の十分小
さい値に制限することにある。The present invention is a switch driving signal generating circuit K11 which is necessary for this type of device.The purpose of the present invention is to enable extremely heavy-duty circuit assembly using commercially available timer ICs, and to short-circuit one load. To automatically limit excessive current at a time to a sufficiently small value below a specified value without providing a separate current limiting circuit.
図WiについてA体的に説明するに、第1図において1
点鎖線ムーA′から左の部分が本発明を実施した駆動信
号発生回路の1例に該当する。該@締の右側上にある出
力変圧器lは1次励磁巻線11%2次出力巻線12及び
電圧波形検出巻線13會有し、1次巻線11は主スィッ
チ素子14と直列になって主属流電11Vlに接続され
る。2次巻線12は整流ダイオードDsと平滑コンデン
サC4の直列回路に接続されs C4と並列に負荷抵抗
RAと出力制御信号電圧発生回j12の電流巻線21と
の直列回路が接続される0回路2Fi出力電流即ちR7
の電流とその規定値との差を検出し、出力値が規定値よ
り小さいほど大になる正の制御信号電圧Vct発生する
ものである0なお巻線11−13の各誘起電圧タイミン
グ回路3に免1j御用直流電源■露の端子間に接続され
る直列充電抵抗gtとコンデンサC1及びこれと並列の
放電用スイッチ素子17f:具備し、その光放電の時定
数が本装置のスイッチ開閉の時間を設定する基準となる
−のである。To explain Figure Wi in A-physical terms, in Figure 1, 1
The portion to the left of the dotted chain line MuA' corresponds to an example of a drive signal generation circuit embodying the present invention. The output transformer l located on the upper right side of the @fastening has a primary excitation winding of 11%, a secondary output winding 12 and a voltage waveform detection winding 13, and the primary winding 11 is in series with the main switch element 14. and is connected to the main current 11Vl. The secondary winding 12 is connected to a series circuit of a rectifier diode Ds and a smoothing capacitor C4, and a series circuit of a load resistor RA and a current winding 21 of the output control signal voltage generation circuit j12 is connected in parallel with C4. 2Fi output current i.e. R7
Detects the difference between the current of A series charging resistor gt, a capacitor C1, and a discharging switch element 17f connected in parallel with the series charging resistor gt and the capacitor C1 are connected between the terminals of the DC power supply for commercial use. This is the standard to be set.
上記検出巻線13に接続される同期パルス成形に4賂1
5は尚抵抗R4と整流ダイオードD!の直列回路及び1
t4とD!の接合点しから分岐してD雪と並列に警絖さ
1するコンデンサCaと低抵抗Rsの直列回路から敗り
、CmとR8の接合点(は回路15の出力点となるoc
sRil路は做分回路を構成し、従って入力点数にふ・
ける父査篭圧はDtに工り整流されて仮似分さ100点
気λ1出カバ、ユとパ現ゎ。63゜上記コンデンサCI
g)正側端子点Pかも分岐するコンデンサ充放−回路1
6はCIと並列に接続される!1泥ダイオードDiと高
抵抗R2の直列回路及びDlとR1の接合点dと前記出
力点Cとの間に接続宴詐るコンデンサC2から成り、点
dは@路l藝O出力点となる◎回路Dt −C2はこれ
に前記のt抵抗Rsも直列に入れて、clの充電期間中
その充電に連動的に追従してCtが充電される連動充電
回路管構成し、回路R重−Cm社R1も入れて、Ctが
一時に放電したと亀高抵抗R−故にCtが緩慢に放電す
る遅燵放電回路を構成する。4 wires 1 to synchronous pulse shaping connected to the above detection winding 13
5 is a resistor R4 and a rectifier diode D! series circuit and 1
t4 and D! The junction of Cm and R8 (oc is the output point of circuit 15) is branched from the junction of Cm and R8 and connected in parallel with D from the series circuit of capacitor Ca and low resistance Rs.
The sRil path constitutes a dividing circuit, and therefore the number of input points is
The primary pressure that is generated is rectified by Dt, and the tentatively divided 100 points are λ1. 63゜Above capacitor CI
g) Capacitor charging/discharging circuit 1 branching from the positive terminal point P
6 is connected in parallel with CI! It consists of a series circuit of a diode Di and a high resistance R2, and a capacitor C2 connected between the junction point d of Dl and R1 and the output point C, and the point d becomes the output point. The circuit Dt-C2 has the above-mentioned t resistor Rs connected in series to form an interlocking charging circuit tube in which Ct is charged in conjunction with the charging of cl during the charging period, and the circuit R-Cm is R1 is also included to form a slow discharge circuit in which when Ct is discharged at once, Ct is slowly discharged due to the high resistance R-.
総会回路4はタイミング回路3の出力点P及び回路l−
の出力点dかもの各出力電圧を受けて、他方前記出力制
御信号電圧発生回路2からの制御電圧■。に応じてスイ
ッチ素子14の開閉のための駆動1号を発生する回路で
ある。この回路は通常はIC化されているが、図tii
はその機能を郷価的なブ■ツク図として懺わし九もので
ある。第1電圧比較回路5ue−)及び(イ)各入力と
して点Pからの電圧■p及び上記制御電圧Vat夫々与
えられ、その出力は微分回路8を経てフリップフルツブ
回路7のり竜ツシ入力鼠へ与えられる。第2の電圧比較
回路6はH及び出各入力として制御電圧V。を電圧分割
回路R,−R,て適当な比率に分圧した電圧■を及び点
在からの電圧VaVt与えられ、その出力は上記日11
7e*ット入力Sへ与えられる0回路7の竜ット出力Q
はスイッチ素子14の制御点へ与えられ、他方リセット
出力Qは01の短絡用スィッチ素子170制御点へ与え
られる。The general circuit 4 connects the output point P of the timing circuit 3 and the circuit l-
The control voltage (2) from the output control signal voltage generation circuit 2 receives each output voltage from the output point d. This is a circuit that generates drive No. 1 for opening and closing the switch element 14 in response to the following. This circuit is usually implemented as an IC, but in Figure tii
presents its functions in the form of a popular book diagram. The voltage ■p from point P and the control voltage Vat are given as inputs to the first voltage comparator circuit 5ue-) and (a), respectively, and the output passes through the differentiating circuit 8 to the input terminal of the flip-flop circuit 7. Given. The second voltage comparator circuit 6 receives a control voltage V as an H and output input. The voltage dividing circuit R, -R divides the voltage to an appropriate ratio and the voltage VaVt from the dots is given, and its output is as shown in the above day 11.
7e*t output Q of 0 circuit 7 given to input S
is applied to the control point of the switch element 14, while the reset output Q is applied to the control point of the short-circuit switch element 170 of 01.
第1図に示す装置の?¥mについて説明する0巻$1i
113に誘起する点1の電圧は第2図の曲線a[示すよ
うな波形で、時刻tlからt!の関はスイッチ14の開
期間で正極性の大きな跳返シミ圧が現れる。t!からt
$の間はスイッチ14の閉期間で負極性の略一定振幅の
波形となる0第1図の点すにおける電圧波形は抵抗R4
とダイオードDaのため第2図の曲Ml)K示すように
同図曲線1の正部分が振幅制限された破線のような波形
となる。この波形をH路Cs Raで微分すると第2
図の曲線Gで示すように波形すのゼロクロス点で発生ス
るパルス波形が第1図の出力点Cに生ずる。この中で負
極性のみが同期パルスとして用いられる。What about the device shown in Figure 1? Volume 0 $1i explaining about ¥m
The voltage at point 1 induced at point 113 has a waveform as shown in curve a in FIG. 2, from time tl to t! At this point, a large rebound stain pressure of positive polarity appears during the open period of the switch 14. T! From t
During the period of 0, the voltage waveform at the point 0 in FIG.
Because of the diode Da and the diode Da, the positive part of the curve 1 in FIG. 2 has a waveform like a broken line with limited amplitude, as shown by the curve Ml)K in FIG. When this waveform is differentiated by the H path Cs Ra, the second
As shown by curve G in the figure, a pulse waveform generated at the zero-crossing point of the waveform is generated at output point C in FIG. Among these, only the negative polarity is used as a synchronization pulse.
総合回路4内において、フリップ7aツブ回路0ン γがリセット状態にあるときはそのQ出力はQ。In the general circuit 4, the flip 7a tube circuit 0 When γ is in the reset state, its Q output is Q.
Q出力はl(正の出力)であるから、スイッチ14は開
、スイッチ17は閉状態であり、従ってコンデンサC1
の電圧は殆んどゼロである。そこで今回路7が入力Sの
附勢にょリセットされたとすれば、Q出力Fil、Q出
力は0となるので、スインf14は閉じて巻線11に励
磁電流が流れ始め、同時にスイッチ17Fi開いてコン
デンサCs#i電IGi Vgから抵抗Rxff1経て
流nる電流に1って充電され%C1の端子電圧■pに第
4図に示すように上昇を始める。Since the Q output is l (positive output), the switch 14 is open and the switch 17 is closed, so the capacitor C1
The voltage is almost zero. Therefore, if the circuit 7 is now reset to the energization of the input S, the Q output Fil and the Q output become 0, so the switch f14 is closed and the excitation current starts flowing to the winding 11, and at the same time, the switch 17Fi is opened and the capacitor Cs#i is charged by the current flowing from IGi Vg through resistor Rxff1 and begins to rise to a terminal voltage of %C1 as shown in FIG.
このとき絡1図において点dの電圧Vaも■1に従って
第4図破線のように上昇する。At this time, the voltage Va at point d in Figure 1 also rises as shown by the broken line in Figure 4 in accordance with 1.
電圧比較回路50両入力についてV、<V。の関はその
出力は正の一定値であるが、■1が■。K吟しくなった
瞬間に絞出力は負の値に急変する。この出力は回路8で
微分されてフリツプフロツプ回路70B入力に与えられ
、この回路をリセットする。よってスイッチ14tl−
き、スイッチ17は閉じるO従ってC1の寛iは急速に
放電し、Vp1ユ第4図に示すように急にゼ■に近い値
に低下する。Voltage comparator circuit 50 For both inputs, V, <V. The output of the function is a constant positive value, but ■1 is ■. The moment the aperture becomes sharp, the aperture output suddenly changes to a negative value. This output is differentiated by circuit 8 and applied to the input of flip-flop circuit 70B to reset this circuit. Therefore, switch 14tl-
Then, the switch 17 closes. Therefore, the voltage of C1 is rapidly discharged, and Vp1 suddenly drops to a value close to zero as shown in FIG.
しかしCtに充電された電荷FiDtが逆バイアス状態
にある大めすぐKは放電しないで■cLはRxCg
の時定数で(Rs < R舅)第4wAM線のようにゆ
つく9降下する。However, as soon as the charge FiDt charged in Ct is in a reverse bias state, K does not discharge ■cL is RxCg
With a time constant of (Rs < R), it slowly descends like the 4th wAM line.
苔し11路15からの同期パルスがC!を介して点al
(加tられなければ、vdは比較回路6のH入力電圧V
jに郷しくなるまで降下を続ける。V、1がVzに等し
くなると、比較回路6の出方は正から負に急変して微分
回路9を経て回路7の8人力に与えられるので回路7を
セットし、すべては最初の状態に戻り、再び上記の動作
を反復することになる。The synchronized pulse from Kokeshi 11 and 15 is C! via point al
(If t is not added, vd is the H input voltage V of the comparator circuit 6
Continue descending until you feel at home. When V, 1 becomes equal to Vz, the output of comparator circuit 6 suddenly changes from positive to negative and is applied to circuit 7 through differential circuit 9, so circuit 7 is set and everything returns to its initial state. , the above operation will be repeated again.
しかし屯営の動作状態では第4図の時刻t1でスイッチ
14が開くと巻!113には第2図示のような跳返り電
圧が発生し、そのゼロクロス点において同図の曲lac
のような振幅の比較的大きな同期パルスカ現れ、こnは
コンデンサCtt経て点aに伝えられ、電圧Vdは第5
図に示すように時刻tlて一時Vz以下になるため、比
較回路6が作動してフリップフロップ回路7がセットさ
れ、この時点て最初の状態に戻る。tQとtlの間がス
イッチ14の閉期間Toであり、tlとt2の間が開期
間Tfである。However, in the operating state of the camp, when the switch 14 opens at time t1 in FIG. 113, a rebound voltage as shown in the second figure is generated, and at the zero cross point, the curve lac in the same figure is generated.
A relatively large synchronous pulse appears with an amplitude such as n, which is transmitted to point a via capacitor Ctt, and voltage Vd is
As shown in the figure, at time tl, the voltage temporarily becomes lower than Vz, so the comparator circuit 6 is activated and the flip-flop circuit 7 is set, and at this point the voltage returns to the initial state. The period between tQ and tl is the closed period To of the switch 14, and the period between tl and t2 is the open period Tf.
制御電圧■。の大きさが変わるとTnは変化するが、T
t4n常に跳返り電圧波形幅に一致してお)、系の動作
が安定に行われる。Control voltage■. Tn changes when the size of changes, but T
t4n always matches the rebound voltage waveform width), the system operates stably.
本装置の特徴は負荷短絡時の電流が自動的に安全な小さ
い値に制限され、短絡が解けると直ちに正常動作に戻ゐ
ことである。次にその理由を説明する。負荷短絡又はそ
れに近い状lIKなると、出力電流は正常値より遥かに
大になるので、回路2の出力■。は殆んどゼロとなり、
スイッチ14の閉時間を最小にし、出力電圧従って短絡
電流全減小するように動作する。しかし通常回路4が正
常動作管する■cの最小値には限界があり、そのためス
イッチ14の閉時間幅量ゼロKまて近づけることはでき
ない。そのため上述の正常な電流制御機能のみでは短絡
電流を充分小さくすることが困@になる。本装置の回路
では負荷短絡又はそれに近い状態ではC4の端子電圧は
正常値よシ搗かに小になるので、巻1!12に現れる跳
返9電圧の振幅もC4の電圧で小振幅に抑制される。従
って巻1113の電圧も第1図の曲線aに示すように小
になる。そのため(四りロス点付近での波形の傾斜は図
示のように非常に験かに&る。従ってこの波形會微分し
た第1図の点Cにおける電圧波形も第3図の曲laCの
ように負の振幅が小になる。そのため跳返)電圧の最初
のゼロクロス点t8ではVa h V7よシ相当大であ
るから、点Cにパルスが加わっても比較回路6Fi作動
しない。跳返や電圧は減衰振動波形となるので、その俵
に発生するパルスは更に小振幅になる。従ってVdが■
を近くの値に低下するまで比較回路6は作動せず、スイ
ッチ14の開期間は正常動作の場合より非常に長くなる
。回路60人力抵抗が高ければ抵抗R1の値も大きくで
きるため、VdO滅真の時定数CtRx k大に選ぶこ
とが可能でろ’)sVaの減衰曲線の傾斜會緩やかにし
て上記の開期間を光分大にし、毎秒当夛のスイッチの1
閉口数を小にして出力匂絡ttIL會充分小さい値に自
11ノ的に制限することができる。なお短絡が解除され
ると自動的に正常動作に復帰することは明かである。The feature of this device is that the current is automatically limited to a safe small value when the load is short-circuited, and normal operation resumes as soon as the short-circuit is removed. Next, the reason will be explained. If the load is short-circuited or close to it, the output current will be much larger than the normal value, so the output of circuit 2 will be becomes almost zero,
It operates to minimize the closing time of the switch 14, thereby reducing the output voltage and therefore the short circuit current. However, there is a limit to the minimum value of c for which the circuit 4 normally operates, and therefore the closing time width of the switch 14 cannot be brought close to zero K. Therefore, it is difficult to sufficiently reduce the short-circuit current using only the above-mentioned normal current control function. In the circuit of this device, when the load is short-circuited or in a state close to it, the terminal voltage of C4 becomes much smaller than the normal value, so the amplitude of the rebound voltage appearing in windings 1 and 12 is also suppressed to a small amplitude by the voltage of C4. be done. Therefore, the voltage of winding 1113 also becomes small, as shown by curve a in FIG. Therefore, the slope of the waveform near the four-way loss point is very uncertain as shown in the figure.Therefore, the voltage waveform at point C in Figure 1 obtained by differentiating this waveform also becomes curve laC in Figure 3. The negative amplitude becomes small.Therefore, at the first zero-crossing point t8 of the rebound voltage, it is considerably larger than Va h V7, so even if a pulse is applied to point C, the comparison circuit 6Fi does not operate. Since the bounce and voltage form a damped oscillatory waveform, the pulse generated in the bale has an even smaller amplitude. Therefore, Vd is ■
The comparator circuit 6 is not activated until the value of 0 is reduced to a value close to 0, and the open period of the switch 14 is much longer than in normal operation. If the human resistance of circuit 60 is high, the value of resistor R1 can be increased, so it is possible to select a large VdO extinction time constant CtRxk. Turn on the switch and hit the switch every second.
By reducing the number of closures, it is possible to limit the output voltage ttIL to a sufficiently small value. It is clear that normal operation will be automatically restored when the short circuit is removed.
以上は制御伽号亀圧■。が負荷電流に応動して自動的に
変化する場合について述べ友が、変型として電圧■。が
出力検出回路2とは関係なく独立に外部から与えられる
場合にも本装置の短絡電流制限の機能に支障のないこと
は明かである。The above is the control word turtle pressure■. A friend mentioned the case where the voltage changes automatically in response to the load current, but as a variation of the voltage ■. It is clear that there is no problem with the short-circuit current limiting function of this device even if the voltage is applied from the outside independently of the output detection circuit 2.
次に本装置による短絡電流制限効果の14P4會述べる
。出力定格電流05mム、電圧約5000Vのこの種電
源装置において、本発明によらない場合即ち短絡が生じ
てもスイッチ14の開期間が殆んど変化せず、閉期間の
み最小値となるように制御さn%他に特別な電流制限の
手段が講ぜられていない場合には短絡電流を数mA以下
に制限することに困難である。然るに本発明による同定
格の装置では短絡電流t1mA以下に制限できた。Next, the 14P4 session will discuss the short-circuit current limiting effect of this device. In this type of power supply device with an output rated current of 05 mm and a voltage of about 5000 V, the open period of the switch 14 hardly changes even if the present invention does not apply, that is, a short circuit occurs, and only the closed period becomes the minimum value. If no other special current limiting means are taken, it is difficult to limit the short circuit current to a few mA or less. However, in the device of the present invention with the same rating, the short circuit current could be limited to t1 mA or less.
以上の説明から明かなように本発明の駆動回路は市販の
ICその他の部品を用いて容易にしかも安価に製作する
ことができ、変換装置の動作音安定にし、災に負荷短絡
時に′s?社る電流を別個の電流制限回路を設けずに十
分Iトさな僅に自動的(制限し、また短絡解除のとik
Kは自動的に正′ItwJ作に復帰する特徴を持ってい
る。As is clear from the above description, the drive circuit of the present invention can be manufactured easily and inexpensively using commercially available ICs and other components, stabilizes the operating sound of the converter, and prevents the drive circuit from causing a load short-circuit. The short-circuit current can be limited automatically without a separate current-limiting circuit.
K has the characteristic of automatically returning to the original 'ItwJ' work.
常勤炸時の各点の電圧波形図、第3図は負荷短絡時の同
様な波形図、第4図は同期パルス久方のない場合の各点
の電圧波形図、第5図は該久方のある場合の同様な電圧
鼓形図である。
l:tB力変圧器 13:電圧波形検出巻線2
:出力制御信号電圧発止回路
3:タイミング回路 5.6=電圧比較回路7:7リ
ツプ70ツブ回路
14.17:スイッチ素子
15:同期パルス成形回路
16:コンデンナ充放電回路
代理人 弁理士 上 山 操The voltage waveform diagram at each point during full-time bursting, Figure 3 is a similar waveform diagram when the load is short-circuited, Figure 4 is the voltage waveform diagram at each point when there is no synchronized pulse, and Figure 5 is the voltage waveform diagram at each point when there is no synchronous pulse. FIG. 6 is a similar voltage hourglass diagram for the case of FIG. l: tB force transformer 13: Voltage waveform detection winding 2
: Output control signal voltage starting circuit 3: Timing circuit 5.6 = Voltage comparison circuit 7: 7 lip 70 tube circuit 14.17: Switch element 15: Synchronous pulse shaping circuit 16: Condenser charging/discharging circuit Agent Patent attorney Kamiyama Miscellaneous
Claims (1)
スイッチ素子との並列回路を接続したタル電圧波tlR
形微分してそのゼロクルス点でパルス會発生するように
構成した同期パルス成形回路、上記タイミング回路のコ
ンデンサと並列Kl流ダイオードと抵抗との直列回路’
ii続してこれら両者の接合点と上記同期パルス成形回
路の出力点との間にコンデンサ會接続し該接合点を出力
点とするコンデンナ充放電H路、 上記タイミング回路の出力電圧と出力制御信号電圧1両
入力とする第1電圧比較回路、上記出力制御信号電圧會
適JfiK分圧した電圧と上記コンデンナ充放電H路の
出力電圧を両入力とするg雪電圧比較回路、並びに 上記第1及び第2電圧比較回路の各出力を受けて交互に
作動するフリップフロップ回路會具備し、該フリップフ
ロップ回路のセット及びリセット舎出力會夫々出力変圧
器の1次巻線と直列のスイッチ素子及び上記タイミング
回路の放電用スイッチ素子の各制御点へ接続して成るス
イッチング型直流変換装置の駆動回路。[Claims] A tall voltage wave tlR in which a parallel circuit of a capacitor and a discharging switch element is connected in series with a charging resistor between DC power supply terminals.
A synchronous pulse shaping circuit configured to generate a pulse at its zero-cruise point by differentiating the shape, and a series circuit of the capacitor of the timing circuit, a parallel Kl flow diode, and a resistor.
ii) A capacitor charge/discharge H path that connects a capacitor between the junction of these two and the output point of the synchronous pulse shaping circuit and uses the junction as the output point; and an output voltage and output control signal of the timing circuit. a first voltage comparator circuit having one voltage input; a g-snow voltage comparator circuit having both inputs the voltage obtained by dividing the output control signal voltage JfiK and the output voltage of the capacitor charging/discharging H path; A flip-flop circuit is provided which operates alternately in response to each output of the second voltage comparator circuit, and a set and reset circuit of the flip-flop circuit is provided with a switch element in series with the primary winding of the output transformer and the above-mentioned timing. A drive circuit for a switching type DC converter that is connected to each control point of a discharge switch element in the circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7158682A JPS58190277A (en) | 1982-04-30 | 1982-04-30 | Drive circuit for switching type dc converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7158682A JPS58190277A (en) | 1982-04-30 | 1982-04-30 | Drive circuit for switching type dc converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58190277A true JPS58190277A (en) | 1983-11-07 |
| JPS6366157B2 JPS6366157B2 (en) | 1988-12-19 |
Family
ID=13464930
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7158682A Granted JPS58190277A (en) | 1982-04-30 | 1982-04-30 | Drive circuit for switching type dc converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58190277A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6149657A (en) * | 1984-08-15 | 1986-03-11 | Canon Inc | power supply |
| JPS6149656A (en) * | 1984-08-15 | 1986-03-11 | Canon Inc | Power unit |
-
1982
- 1982-04-30 JP JP7158682A patent/JPS58190277A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6149657A (en) * | 1984-08-15 | 1986-03-11 | Canon Inc | power supply |
| JPS6149656A (en) * | 1984-08-15 | 1986-03-11 | Canon Inc | Power unit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6366157B2 (en) | 1988-12-19 |
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