JPS58196610A - magnetic disk device - Google Patents

Abstract

PURPOSE:To prevent a reproduction error of data owing to a peak shift despite high recording density, by varying the timing compensation degree to a write data in response to the position of a track to which a data is written. CONSTITUTION:In a data writing mode, a bit serial data input 4 given from a processor, etc. is fed to a shift register 1. Then the timing is compensated for compensation of a peak shift through a timing compensating circuit 2. At the same time, the circuit 2 gives a switch control to the timing compensation degree to the write data in relation to the position of a writing object track in response to a control signal 103 which is delivered from a head address circuit 18. Then the write data is written to a disk 15 through a writing/reading circuit 6, a signal line 7 and a head 14. In such a way, the satisfactory compensation is possible for the peak shift over the entire region of the disk. Thus, the reproduction error of the data owing to a peak shift is prevented despite high recording density.

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention relates to a magnetic disk drive, and more particularly to tiling correction of written data to compensate for peak shifts during data reproduction.

2. Description of the Related Art In order to compensate for peak shifts, there is a magnetic disk device that has means for applying timing correction to written data during data writing. However, in the conventional magnetic disk device C2 of this type, the above-mentioned timing correction means is configured to perform timing correction on the stored data without considering the position of the write target track on the disk. Therefore, as recording ff1lf increases, a problem arises in that sufficient peak shift compensation cannot be achieved.

OBJECTS OF THE INVENTION An object of the present invention is to provide a magnetic disk device that can perform good peak shift compensation (two lines) even when recording density is high.

In consideration of the fact that the peak shift value changes by a considerable amount (1fil) between the tracks on the outer circumference of the disk and the tracks on the inner circumference side, in the present invention, the write data is changed depending on the track position of the target track. 2. The timing correction means is configured so as to change the timing correction position to be applied.

More specifically, the timing correction means of the magnetic disk device according to the present invention, for data written to a track outside a specific track position on the disk, writes data to a track inside the specific track. It is configured to reduce the amount of timing correction for data (or to prohibit timing correction for data convolved in a trough outside the track position).

Embodiment of the Invention FIG. 1 is a schematic configuration diagram showing the overall configuration of a magnetic disk device that is an embodiment of the invention.

In the figure 4, (5 is a disk, which is constantly rotated by the motor 16, data is convoluted by the head 14, and φ6
is the outer recording surface 1 on the disk 15 shown in FIG.
5m, and the head 14's φ1. φ3. φ5. φ7 is attached to the head arm 13 in correspondence with the inner recording surface 15b on the disk 15, and the voice coil motor 11. It is positioned at an arbitrary track position within a corresponding recording surface by a driving section consisting of a carriage 12, and data is loaded and read out.

During data convolution, bit-serial data input 4 from host devices (not shown) such as a processing device and a control device is manually inputted to a shift register 1, and a timing correction circuit 2 is used to perform peak shift compensation. Corrections are made.

A feature of the present invention is that the timing correction circuit 2 switches and controls the timing correction amount for the write data (2) in accordance with the control signal 103 output from the head address circuit M18 in relation to the write-R11 track position (2). However, I will explain it later.
1. Now, the write-in data that has been subjected to timing correction and is sent to the data output 5 of the timing correction circuit 2 is the same as the conventional one (2. write/read circuit 6, signal line 7,
The disk disk 15 (: is written through the head 14.

When reading data, the data stored in the disk inner plate 154 is output from the head 14 and sent to the host device through the signal line 7, continuous write circuit 6, signal line 8, phase synchronization circuit 9, and signal line 10. Transfer.

The phase synchronization circuit 9 receives a servo signal from another disk and its corresponding head (both not shown), generates a clock 3 during recording, and performs data discrimination and read data manually during reading. Corrects a certain signal line 80 pit deviation. Immediately before inputting and outputting the data (; the host device passes the signal line 17 through the signal line 17 to select one of φ0 to φ7 of the L-C head 14. Based on this signal, the head address circuit 18 selects the head 14 through the signal line 19 and also generates the control signal 103 described above.

Figure N&3 shows the relationship between the recording pattern at the time of data writing and the reproduction pattern ζ at the time of data writing: the width of the frequency and the peak shift track. In C= of the same figure, TW indicates a recording frequency of 1-1 Tp indicates a peak shift.

It is known that in the case of the Mi'M recording system, the TW changes by a factor of 3, 4, 5, 6, and in some other polar recording systems, it changes by a factor of 3 to 8. Even in both recording methods, the TW is different between the outer recording surface 15a and the inner recording surface 15b in FIG. The ratio of TW between the Ill outer track and the innermost track is approximately 1.6:1
), there is. However, conventionally, the timing correction circuit performs timing correction without taking such TW changes into account, so that the write/read circuit 6, head 14, etc.
In the case where the recording surface has a polarity, there is a drawback that the compensation for the peak shift is excessive on the outer recording surface and insufficient on the inner recording surface. As mentioned above, the object of the invention is to eliminate this drawback and to enable sufficient peak shift compensation even in the case of high recording density.

An example of the shift register 1 and timing correction circuit 2 in FIG. 1 is shown in FIG. 4, and details of the timing correction operation for write data will be explained.

21 to 27 are flip-flops (abbreviated as FF), and as shown in the figure, two are connected in series to form a 7 register. (The write h data is clock 3
At the timing of FF'll, the FF26.
25.24.23.22.21. Further, the timing correction circuit 2 includes AND circuits 41 to 45, O
H circuit 50, delay circuits 31, 32, and inverter 5
It consists of 1. The AND circuit 41 receives the control signal 1.
03, FF21. Sae's Q output, m of FF'll's q output
Take the filling and A N D I11? ]Wr 42 is FF
'21.2'l Q output, a signal obtained by delaying the Q output of F F 24 by the delay circuit 31, and the control signal 103! 1
iii Take the burial. AND circuit wr43 is the output of the delay circuit 31, the Q output of FF21, 27, and the control signal 103.
ii! I, take the product, ANi) The circuit 44 is -m:
The output of the delay circuit 31 is further delayed by the delay circuit 32, the Q output of i1'F21, the Q output of Fk''71, and one end of the control signal 103 are taken. A signal obtained by embedding the outputs of these ANI circuits 41 to 45 in an OH circuit 50 is outputted as a data output 5.

The control signal 103 sent from the head at Vs circuit 18 (Fig.
1. φ3. 5. When any of φ7 is specified for 1 inclusion, it is set to ON @1″N-), outside 11
J regiment side 15a+:, corresponding Heradna 0. S2, S4.
Turns off when 5w is added to any of φ6. When the image control signal 103 is turned on, the output of the FFs 21 to 27 outputs the data output 5 (the Q output of i"fi"W, a signal delayed by passing it through the delay circuit 1% 31, or two delay circuits). 31. Either of the delayed signals is output through 32. In other words, the timing of the write data changes in three stages depending on the pattern (2), and peak shift compensation during playback and recording timing correction of 1 are applied. Ru.

On the other hand, when the control signal 103 is off, that is, the disk [5
Up to any track in the outer record 1ti15a above =
When data is loaded, a signal obtained by delaying the Q output of iEJ'fi' 24 by the delay circuit 31 is sent out to the data output 51. In other words, timing correction is not performed in this case.

Another example of the timing correction circuit 2 is shown in FIG. #1 data included in surface 15a (timing correction is also applied to #2, but the correction data is transferred to inner recording surface 15
This configuration reduces the amount of data written to b.

Therefore, the timing correction circuit 2 of this example has an AND circuit 4
6~49.52~55.0) 11 closed 50, 56°57
, i4 extension circuits 33 to 36, and an inverter 51. AND circuit 46 connects l+″F2 in shift register 1
Q output of 1.24, FF'l! The AND circuit 47 takes m of the Q outputs of FF21.27 and ORs them with the Q outputs of FF21.27.

@fill with the output of circuit 56. AND circuit 48 is O
The output of the R circuit 56 and the Q outputs of the FFs 21 and 27 are ANDed. The AND circuit 49 takes the AND of the Q output of the FF 21, the Q output of the FF 17, and the output of the OR circuit 57. The AND circuit 52 fills #1 with the signal obtained by delaying the Q output of the FF 24 by the delay circuit 33 and the signal obtained by logically inverting the control signal 103 by the inverter 51. AND circuit 53 receives control signal 1
03 and a signal obtained by further delaying the output of the delay circuit 33 through the delay circuit.

AND circuit 52.53 (F) output cover Oa circuit 5s-c-
*Buried. The AND circuit 54 performs a logical product of the signal obtained by delaying the Q output of the FF 24 by the delay circuit word and the output of the inverter 51. The AND circuit 55 performs a logical product of a signal obtained by further delaying the output of the delay circuit 35 by a delay circuit and the control signal. The output of AND circuits 54 and 55 is O! circuit 5
7Qiiiil compensation is taken.

When the control signal 103 is on, AND circuits 53.55 are turned on, and when it is off, AND circuits 52.54 are turned on.

That is, when the control signal 103 is on, the Q output of the FF 24 is
OR circuit 5 through delay circuit 33 and AND circuit 53
6 or to the OR circuit 57 through the delay circuits 35 and 36 and the AND circuit 55, and when the control signal 103 is off, the signal is input to the OR circuit 57 through the delay circuit 33 and the AND circuit 52.
or through the delay circuit (to the OR circuit 57.The delay time of the delay circuit 33, 36 is 1:2 in advance.
Since the timing of sending write data to data output 5 changes in three stages depending on the output pattern of FF21~, and when the control signal 103 is on and off, data is written to data output 5. The difference in timing of data output is l:2.

Head address circuit 1 that sends out the aforementioned control signal 103
An example of 8 is shown in FIG. 6 and will be explained.

101 is a register, and 102 is a decoder. In order to select and designate one of the first heads 14 (#O to #8), a modulo 3 head selection signal is sent from the host device to the signal line 17, and is sent through the register 101 to the deq-der 102ζ.
: Input. The lowest signal of the register 101 is sent to the timing correction circuit as the aforementioned control signal 103.

The decoder 102 decodes the head selection signal and outputs a signal to one of the signal lines 19 corresponding to the head to be selected.

In the embodiment described above, the timing correction amount of the timing correction circuit 2 is switched and controlled by the outer recording surface 15a and the inner recording surface L5b on the disk 15, but the disk 15 is further divided into three or more thin recording surfaces. , the timing correction amount may be switched and controlled for each recording.

Effects of the Invention As detailed above, according to the present invention, the timing correction tV for the written data is changed depending on the target track position for data writing, so that peak shift compensation can be sufficiently performed over the entire disk area. This makes it possible to prevent data reproduction errors due to peak shifts even when the recording smoothness is uneven.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram showing an example of the overall configuration of a magnetic disk device according to the present invention, FIG. 2 is a perspective view showing the outer and inner recording surfaces on the disk, and FIG. 3 is a recording pattern and reproduction A diagram showing the relationship between the width of the recording frequency and the amount of peak shift depending on the pattern, Figures 4 and 5 are block diagrams each showing an example of separate arrangement of the timing correction circuit, and Figure 6 is a block diagram showing an example of the head address circuit. It is a diagram. DESCRIPTION OF SYMBOLS 1... Shift register, 2... Timing correction circuit, 6... Write/read circuit, 9... Phase synchronization circuit, 11
...Voice coil motor, 12...Carriage, 1
3...Head am, 14...Head, 15...Disk disc, 18...Head address circuit, 21-2
7...Flip-flop, 31-36...Delay circuit, 41-49.52-55...AND circuit, shame, 56
...ORl1g1 path, 101...Register, 102
···decoder. Representative Patent Attorney Susuki 1) Yukihito Tori, c,”,, Jyj 5?2 Figure 25

Claims (2)

[Claims] (1) In order to compensate for peak shifts when reading data from a disk, data is written during data writing (in magnetic disk drives that have a timing correction means for correcting the timing of data written in two bins). 1. A magnetic disk drive, comprising: means for generating a control signal related to a track position, and said timing correction circuit is configured to change a timing correction for data for cutting down in accordance with the control signal. (2) The timing correction circuit corrects timing correction wrinkles when reproducing data from tracks outside a specific track position on the disk when the control signal is high, to tracks inside the specific track position. #Ii according to claim 1, characterized in that control is performed smaller than that of the timing correction type for write data to
i-disc device.