JPS58201347A - Leadless chip parts and preparation thereof - Google Patents

Abstract

PURPOSE:To obtain a structure which is convenient for production and mounting by preparing for different planes for element mounting and providing external plane terminals and connecting these planes through a through hole. CONSTITUTION:A substrate area part C is a substrate 27 of a chip part 25 and external plane terminals 17, 18 of each electrode are located at the opposing plane to the chip element 22 mounting plane through a conductive layer 19 which is extending vertically on both edges of substrate formed at the conductive layer on the internal wall of through hole. With such a structure, it is no longer necessary to place the chip parts upside down at the time of mounting. Therefore, even if a photo transistor and an LED are selected as element 22, a conductive layer pattern is not influenced thereby. Such structure is capable of simplifying the production process because division or cutting is possible for each chip in the final process.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a leadless (leadless) chip component for an electric circuit, and a method for manufacturing the same.

Recently, electronic and electrical components called chip components or mini-mold components, which do not have leads and instead have planar external terminals along the outer surface of the component, have become widely used, especially for hybrid integrated circuits. . The types include passive collectors, J) electric components such as a resistors, conductors, coils, etc.

Electronic components such as various diodes, transistors as active elements, I! This extends to the integrated circuit K.

When referring to these types of parts, it is common to refer to them as chip parts, and this book also follows this.As is well known, chip parts are soldered onto printed circuit boards by reflow, injection, or dip methods. Since it is easy to install and automate, it is very convenient for the user, and since it is extremely small, it is possible to increase the integration density of hybrid integrated circuits, and it is suitable for high frequency applications because it does not have leads! It has many effects such as improving 1♀ properties. However, the conventional one, D41! I-chip parts are not necessarily easy to manufacture from a manufacturer's perspective, and have the disadvantage of requiring complex and extremely precise manufacturing processes, limiting production efficiency, and increasing costs. .

In order to ignore these shortcomings, we have created a mini-7 as a cup part! The production of Red Vibrator/Dista by a conventional method will be explained with reference to FIG.

As shown in Figure 1A, a plurality of fi (generally a very large number)
If you have prepared a base material l made of ceramic or the like with an area that will allow you to create a chip component of
lIj A small board of
It is divided into ... (Rattan 1 Diagram B).

Hereinafter, J)-111 will be selected and explained. The cut-out Kutani substrate is subjected to the necessary processing to produce the substrate J having the required Yasuda-sugi shape as shown in Figure C of ls1. In the transistor taken as an example here, the dimensions of this valley substrate are round and round in both length and width, and the thickness is also extremely small.

First, a conductive layer with a predetermined pattern is formed by vapor deposition or other methods on the surface of the substrate J on which the transistor elements are mounted (this is called the surface). In this example,
Future transistor element t- on the flat part of the center of the board
The mounting surface is the striped single-layer conductor α, and among the four legs standing at the four corners of the board, there are no steps! ia, jg J
) The second conductive layer Q, #b, which connects from the 1st surface through the inner 1# surface and the second conductive layer Q, #b, and one of the two remaining legs &, 6J) From the top surface to the step surface A third conductive layer (C) that stays at the top surface and a fourth conductive layer (FIG. 1D) that stays at the upper surface or step surface of the 1cO are formed on the other hand.

After that, a transistor element group is mounted on the main surface conductive layer dummy with the collector generally in contact with it.1. The emitter is connected to the step surface r′1 outside the third conductive layer, and the base is connected to the fourth conductive layer.
Section 7~: Connect each wire (Fig. 1E).

At the end K, in each conductive layer da b, da C, da d, the leg part *
! ;Cr Hold each upper surface part of 3d in the shape of 4 and mold the element number with a suitable material such as ebokki 74 fat.
As shown by 1a7, the chip component 1 as a mini mold bipolar transistor is thus completed.

When in use, each exposed surface wipe portion becomes an external terminal (in this case, terminal llb).

1) t-x collector end f, 'lc is emitter terminal 5da d
From the FD state shown in FIG. 1, press each terminal 9 times to apply pressure to the desired pattern portion on the hybrid integrated circuit. No, this kind of chip parts are LI
D (Laadlazz Ihvartgd DavL
cg: leadless invertinod device)
It is called. However, the number, arrangement, and shape of the terminals will vary depending on the type of brass and element 6.

The chip parts shown in the second figure are the same (even in the conventional example, one child)
It is composed of IIcr'Id and a molded part 7, and the terminal surface protrudes outward from the molded part.

As for the manufacturing procedure, dozens of sets of leads are arranged on one lead frame, and assembly and molding operations are performed frame-oriented.

However, first of all, if we look at the chip components with the structure shown in Figure 1, we can see that at the initial stage, the same number of substrates for each chip...1...
The work efficiency is extremely poor, as processing, conductive layer creation, chip element mounting, and molding work must be performed on this extremely small board. Even if each process is automated, it is necessary to align and automatically feed such small substrates (or geometrically shaped substrates J) in the correct direction, which requires sophisticated positioning, feeding means, etc. However, the conventional structure shown in the M2 diagram has relatively good workability, but requires expensive auxiliary equipment, and without it it would be impossible to put it on the production line. , it is not possible to increase the packaging density.

As mentioned above, the present invention was developed to solve the inherent production and mounting disadvantages of chip components with conventional configurations, and provides an extremely convenient structure. I'm trying.

Incidentally, in chip components of conventional structure, the mounting surface of the element number and the corresponding terminal surface of the external planar terminal tab face the same direction, so the upper element 6 is used for mounting a circular diode, a phototransistor, etc. If so, use mold resin! ! Although the material is at least transparent to the element, in order to turn it over when mounting it on the printed circuit board, the conductive layer surface 4 ((Z gets in the way, and the light conversion Although there is a drawback that the function is impaired or does not function, the present invention can also improve this.This is because the planar terminal is provided on the surface opposite to the element mounting surface, and the wiring can be done by turning it over. This is because there is no need to attach it to the PC board for use.

In the present invention, a conductive layer pattern for chip elements is provided on the front surface of a substrate of a chip component, and an element 4! is provided on the other surface (back surface or side surface). A required conductor 11LI-pattern is provided as a planar external terminal for the r electrode, and in both butters, the four conductive layer portions to be connected are connected to each other.
To provide a chip component which is connected through a through hole with a conductive layer attached to the inner surface of the board. Guide vt+-
It is said that one through hole with a conductor is hidden as a dedicated one for the -m, v chino 7'l1 product, but in the specific manufacturing method according to the present invention, one through hole with a conductor 'd11- is hidden during the manufacturing process. shared by two or more chip components,
When each chip component is divided, it is divided by a dividing line that hides this through hole with a conductive layer.
A groove-like or flat conductive layer along the 1:F direction.

Through-holes with conductive layers are a technology originally developed for printed circuit boards for wiring. '.

I will explain it in the printed version based on the IXs diagram.

Printed circuit boards for wiring, especially (double-sided printed circuit boards FB (
imaginary line cross section), at c, part of the first part of the clothing, cp,
This technique is used when you want to make a connection between (half cross-section) and the eight-sided conductor layered part cp, (half cross-section).
Drill 4 holes H in both WIc layers cp, , cp, , Cm, and attach a thick layer Hc to the inner surface.
, J) Set the substrate through hole H and the four layers on its inner surface together.
) (In the field of struts, it is called 琳: te through-hole υTl(), and even if it is not specified that it has a rhinoelectric layer, it refers to such a structure.

Therefore, in this book as well, it will be referred to as a single 1c through hole in the following, but there are several known methods for forming the inner conductive layer Hc of this through hole. , a method of forming a double-sided conductive layer cp simultaneously with plating into a desired pattern,
, , cp are formed into a required pattern by normal etching.The conductive conductive layer for holes can be plated separately, and plating methods include electrolytic plating and chemical plating.

In the present invention, as previously stated, the method for forming the through hole itself is not specified in any specific book, and any known method may be used as desired. However, the present invention has succeeded in obtaining various effects described below by incorporating a through-hole structure into a chip component, and the idea is that it is not a diversion of known through-hole technology. be.

Hereinafter, each embodiment of the present invention will be described in detail with reference to FIG. 4 and subsequent figures.

The embodiments shown in FIGS. 84 to 9 show chip components using various semiconductor diodes as elements and methods of manufacturing the same.

First, materials suitable for becoming the substrate for each chip component in the future.
For example, the base material 10 is prepared from materials such as Bakelite, paper phenol, which are inexpensive, glass epoxy, other glass composite materials, and even ceramics, which have poor characteristics.

The area of this base material 10 is set to be large enough to allow chip parts of 11I6I to be cut out in the future. In FIG. 4, the surface of this base material is shown in the lower row 3, and the collected surface is shown in the upper row 3.

When manufacturing a chip component of the present invention using the 'rMb method of the present invention, the cutting or dividing of the base material /θ can be done at the end of the molding process, and batch processing is possible until then.
In FIG. 4, for convenience of explanation, future column direction divisions mXt and row direction division lines are added. Same, base material 1
If you want to effectively use up to the four outer edges of 0, divide in the column direction, v
The number of XtO is Fll-1 for the number J of chips in the row direction (
That is, Xs'', @ = 1, 2, * 111
1 II 11 , rlL-+ ), row direction dividing line η
The number of lines is 1 Roux for the number of chips in the column direction (i.e. η;
) = true, 2. ...-, Le, ) and Nap, if you cut off four sides with the width that forms the outermost periphery of the base material, the dividing line in the 1st column direction is a friend; t = 1゜2, ... , genus +, and
The row direction dividing line η is η;j=1. z, ..., le +1
becomes. In the following examples, the latter is followed, and the substrate area portion for one chip component defined by the column direction dividing line A and the row direction dividing line η and η'1 is expressed as Ci + ). In Figure 4, this unit area portion Ci I and another example, Ci→Le, are shown and this portion is shaded to aid in understanding.

Also, %C11l, Cl1t, ""' CI I n+-
+; C1l I %C,,,11+111@11
, CN #n; ””'; CmI l + C
When describing each of the chip substrate areas mHl, .

Now, the fourth surface will be the surface on which each chip element will be mounted later.
In the figure, on the bottom surface of the base material, there is an I.
) A convenient 4'dt prayer pattern // is formed.

This fruit! ! When looking at each individual chip substrate area C, the conductive layer pattern l/ in example #4 is relatively large for mounting a diode element, and according to TIM Ibo Seine et al. This is followed by a through hole is...0...
A first pattern L6/12 consisting of one edge conductive layer /27) that eliminates the connection to the wire, a wide bonding part conductor 4m/Ja with one side of the diode element, and the previous stripe hole /j. consists of an opposing through-hole IS: one edge wart IU@/, 3h, and a second pattern portion /J extending from the opposite through-hole IS:. Therefore, in this embodiment, the first and second pattern portions/
Ko, /3 is 4 tangent, 2) J! Separate and independent from plate surface #lt part,
It's not that C is provided (but it's okay to have B)
The portion of the substrate area C which is in contact with KvV4 in one column direction (ie, located in an adjacent row in the same example).

No. and C1 + No. s 81U C tonneau +,
The first pattern portion l of one substrate area portion CI,j is shown in Figure IjjE, the substrate area portion C* a )+ in the upper row,
OJl! Ni pattern capital 13 and 44 edge /2b, /34
The second pattern portion 73 of the substrate area portion C1, which is formed by integrally connecting and replacing the parts, is shown in the lower row in the drawing.
4 First pattern portion of contacting board area portion CI+71/
and each end edge /JA, /coh are integrally connected*
lf, LC is here.

Therefore, K, the pair of first and second pattern parts /λ, /3 spanning these two substrate area parts is one pattern //4I
As a result, each division in the row direction Y) (
) ”= 1 s 2 m・φ...+lL+1)
are through-holes t, in this case circular cross-section, aligned in the row direction.
A division #lXj −Xi 1=t that traverses the SD group and also extends the through-hole/S group in the column direction f as well.
('=1+2+...*mt,) Therefore, if the surface of the base material 10 is completely starved, the same,
The v-b patterns are arranged neatly in both rows and columns. Similarly, in the case of the edge portion lcob s /3b that connects with the valley through hole, it is a semicircle with approximately the same width, so one layer that spans between the adjacent board area portions below E. When patterned as a pattern/da, the through-hole opening becomes a ring-shaped conductive layer (/2A, /37)
The wire bonding cap/3a extends from one end in the row direction, and the mechanical bonding cap/sl co. .alpha. extends from the other end in the same direction facing in the diametrical direction.

The pattern 16 of the circumference of the through-hole IS on the layer surface when viewed by turning around is also a ring-shaped four-layered layer around the opening M, but the bottom of the drawing in the 9-direction is The inner half is connected to the wire 1Z in the direction 11 (h7) of the board area through the wire 1Z and the edge part /Ja and the edge part /3b.
Also. A drawing of the evening 1j direction.

The upper hand part/g is connected to the element mounting part λ4 on the surface of the bottom plate area part in the downward direction of the spear and through the carrying part/b'7.
Each will be followed, and later, after going through the D minute mackerel [process, wirebon f I/G l! ! l J) - 10,000 Nui 4 - External surface shape 4 pieces for door opening / 7. Jino's diode on the mounting part side - conventional external planar terminal/1. And...:C.

Same, J) What is the shape of the double-sided planar terminal (/7./za)?

It doesn't have to be semicircular (both circles together).

As shown in the example below, Arashi-0 can be created in any shape.
First, of course, the inner surface of each through hole /j is provided with a conductive layer /f that is continuous in the vertical direction (II! back direction) of the substrate. Conversely, as mentioned earlier, the base material 10i/C is simply mechanically attached with a conductive 4/9f on the inner surface of the drilled hole J, forming what is called a through hole l! in this technical field. is formed.

Tiger back pattern (1/ or /l) as above.

76 and through-hole conductive layer/9t - The present invention does not directly specify the method for forming the layer, and any known method may be used.

As described above, for K, the base material 10 (Q front and back sides, the necessary parts (l and
, iJ and l? Or, if you look at it all together, there are 76)! [l
After forming W & 9 required patterns, 14,
In Fig. 4, only the parts outside the four areas surrounded by the virtual - frame J/ are extracted and enlarged in Fig. S, as shown in m-path 1I6.
Each element mounting portion 12a of a certain board area portion C
Above, an element - in this case a semiconductor diode -
Equipped with At this time, in general, the mounting part /J and the anode or cathode of the EK diode are connected directly, so the other electrode.

It is sufficient if the cathode or anode is connected to the wire ho/te/g/jgK using a wire knife. That is, one diode electrode has a portion It (
(not shown in this figure), and the other diode 'IIt pole is connected to a portion /'IK on the back surface which becomes a planar terminal for this electrode.

After completing the element mounting part on the base material 10, as shown in Fig. 6, the surface side of the base material 10 is completed in one go: C-The molded part is virtually tampered with. ), protects element 6. Although any suitable moryad material may be used, it is natural to select a material that is compatible with the base material 10.

In this way, the molding process was completed. Starting from γ et al., the base material 10 is divided into matrix and each direction dividing line ηl
Therefore, the atL& material is divided or cut. The new method may be mechanical using a cutter, or may be performed using an energy beam such as a laser beam.

Each of the nine parts cut in this manner constitutes a chip diode or a mini-mold diode as a target chip component, as shown in the first figure. J17 of FIG. 8 A-Afi
The board area portion C cut out from the board is the board area of this chip component or chip diode, and each @f of the diode element, the external planar terminal l of the pole, /1
is formed as a conductive layer on the inner wall surface of the through-hole and is located 1 DIIK opposite to the mounting surface of the element via the conductive layer /D, lD which extends in the vertical direction along both edges of the 9-board.

It was. In this manufacturing method, the component # containing the through 1ζ-ru lj
Due to the division of J 41 Yj, each vertical conductive layer /9°/1 has a semicircular groove shape that digs into the body side of the substrate.

Direction 1 Single-sided terminal/7゜it as usual
−? P, conductive layers on both sides in the vertical direction that connect the back conductive layer/
Of course, l, /9 may have a plurality of metal layers and a solder plating layer thereon.

This chip component # (24) is placed on a predetermined conductive pattern saw 9.3θ on a substrate suitable for hybrid integrated circuits.

The mechanical fixing operation is the same as the known method as shown in FIG. 8, and may be performed using a soldering method, a Ditzbing method, or an adhesive medium such as a conductive paste.

The above example is for a two-terminal type Niremen) u Q (However, of course, the front and back conductive layer patterns, number of through holes, position, etc. for the base material 10 and each board core are required in design. If it is a terminal type such as a transistor,
The present invention is also applicable to multi-terminal components such as integrated chip elements. The two embodiments shown in Figures 9 to 12 illustrate such cases.

The same reference numerals are assigned to components corresponding to each component in the second embodiment, and only the suffixes are added or changed depending on the number of suffixes.

The embodiment shown in Figures 9 and 10 is constructed using a mini mold transistor 31 mounted with a three-terminal semiconductor element n such as a bipolar or unipolar transistor as a chip component.

To explain from the static configuration of the gxo diagram, there is a conductive layer on the surface of the board core, which is electrically connected to the back electrode of the board 27, and is provided on one side of the board 27. A connection is made to the inner wall conductive layer /9 of the semicircular groove, which was originally a through pole 73A, through an edge conductive layer l-. , each bonding conductive layer/3a for source,
/3. is provided on the side of the substrate opposite to the - side,
Respectively.

The vertical conductive layer of the quadrant-shaped pain at the corner of this one-rule side/? , /? Edge conductive layer/31. , /3d. This vertical conductivity 1%/?
, /? Also, it was originally a through hole trB, /z
This was the inner wall of the Btv. Each vertical conductive layer/
Each conductor 4#:, /A, /? is connected to 9... and becomes an external planar terminal on the back side of the board. B may be any pattern as described above, and in this case, it is.

A simple version with a circular shape divided is also acceptable. Of course.

Mold material 2II (imaginary line) protects Niremen) Q2.

In this embodiment, on the surface Ic of the substrate 27 of one component, there are three electrically independent conductive layer pattern portions /2, /, ? A, /JB is required.

These three patterns may be formed individually using an appropriate manufacturing method if the present invention is to be used as a product, but the present invention described in detail in the first embodiment described above may be used. In the case of an effective manufacturing method based on batch processing, it is desirable that the surface pattern initially formed on the base material 10 from which a large number of parts can be cut out is a pattern 7 as shown in FIG. In this pattern formation, three types of patterns/41A are formed across the adjacent substrate area C...
, /ψB can be formed regularly, which is advantageous in terms of pattern design and production and effective use of the base material /θ.

In Fig. 9, the areas of the future board areas for each component adjacent in the direction of one row, °Ci - + ', and C4, are indicated by diagonal lines. Considering the area, each element mounting area/
Co a r / co, is the column direction division #i1'X4 between both
One through hole at the top that spans both semicircular parts/
Located symmetrically to NkK.

The respective edge parts / ko h + / ko b together form a through hole /
It surrounds the periphery of jA. Therefore, the second conductive layer for each component/2. / is formed on the base material together with the first pattern / hiromu, and when viewed as a whole, it is arranged in the row direction at every other dividing line in the column direction.

In addition, adjacent dividing lines in the row direction Y) +t, Y)', Y
) and Yj-+ in the column direction.

Next, each through hole lNB, /!fB for each bonding part '3a r /3(, Therefore, each through-hole A//3-B is provided with its center at the intersection with
The area of the substrate area 7C for each of the four chips, which are adjacent to each other in the column and row directions, is covered for a second.

The edge parts of each board area that adopt this through-hole connection /37), /34: /Jd, /Jd are the through-holes A/ /kn f
+7 It is surrounded by a Y-shaped shape.

And each edge portion tB, ts4; ts,1,
ty, 1; then the wire bonding part/J, ,
/J, : /,7. , /Jc are consecutive. In the end, focusing on one through hole ~/1B, , i:Each part of the period/3g, 734: /3k * /JA:
/jte/3. : /74, /3d form the second pattern /ll1l as a whole1(
Become. However, with such a substrate surface pattern, the 14 substrate area portions in each row f that are in contact with each other in the row direction face in opposite directions. Conversely, if we take into account the direction in which each chip substrate area C is adjacent to each other.

-There are three types of putters/ll for sea bream (/ko, /, 7A
.

/JR), when forming a pattern on the base material, two types of butter//dA, /41B, D standard 41J t℃
It will be enough to repeat the arrangement.

The embodiment shown in the 11th and 12th figures is a multi-terminal (hole terminal in this case) integrated circuit chip 33 as a chip component, and although the number of terminals and therefore the number of pattern parts and through holes has increased, the basic There is no difference from the first and second embodiments mentioned above.

The surface f of the board area C for each chip is an integrated circuit chip element with one electrode on the back surface and five electrodes on the top surface, and an element is mounted while electrically connecting with the back electrode depending on the uK. Wire bonding with each of the other five items, including the first pattern portion consisting of the mounting portion/co, the edge portion b, and force plate connecting this to the vertical conductive layer it on the outer surface of the board. Department/, 7. ．． /30. /,
? , , /, 3. , /3i are formed as second to fifth pattern portions /jA - /JE. The respective pattern portions /2, /JA A-/, 71 are.

Respectively, the planar terminal on the back side (the shape is not limited to the same size, but
Here, the shape is a circle divided as described below) /l,
/7 is connected to the inner wall conductive layer /9 of the portion that was originally a through hole. Similarly, a molding material 24 ((virtual #l) covers the element.

In this embodiment as well, each electrode arrangement or pattern part is assumed to be arbitrary, but if the method of the present invention described above is used and the pattern is rationalized and the area of each chip is reduced, the base material 10 Through ingenuity during pattern formation,
Six pattern parts per each chip, /3A~/3
E is second type #4 putter 7 /I as shown in Figure 11
A regular repeating arrangement of A, /daB can suffice.

That is, first, for example, 4a part l, and one D wire pond puffer part/3. The board should be at approximately the same position as the regular side, and the putter/portion containing the remaining four wire bonding parts should be placed at the four corners of the board.
Make sure that the address is received.

Then, pattern w5 juice lko/, 7A K bolted.

In the pre-divided base material 10 J:, as a putter/portion A of the arc centered on one soufflé hole tzh t .

Divide these 13 through holes in each row direction, i! Xs):
In each chip substrate area adjacent in one row direction from K, which is located between a pair of adjacent row-direction divisions, -b: (is part/ko, and the other is IC/'i part/jA t
-I draw by arranging.

For the remaining four parts /3B - /jE K, #! is placed at the intersection of each same-direction dividing line and row-direction dividing line. For each of the four board area parts of each row and column surrounding this through hole /jB, wire holes /3C, /J-+13g, /3B are placed diagonally. If you swing in one direction, you can get away with putting it on the base material/part B. same.

The pattern arrangement of this embodiment is pattern 14 of the first embodiment regarding the pattern/daAK consisting of one part /ko and /jA.
1. The rest of the pattern is an application of the putter 7/#B of the second embodiment.

By the way, in the embodiments so far, the vertical conductive layer l! connects the conductive layer portions in one surface pattern with each other. are relatively small diameter circular through holes /J, /jA, /
Since the inner wall of the JLL is round, the base material 1
In each chip component cut out after the molding process is completed on the substrate 0, each of the conductive layers 19 has a semicircular or quarter-circular cross section that is concave toward the inside of the substrate core. In fact, when K is used like this, it is not only necessary to use the planar terminals /7 and /l on the back side, but also when mounting KN on the printed circuit board for wiring as shown in the figure l1c8.

When the adhering part of solder etc. reaches the conductive layer It on the side of the board, the surface area of the layer/9 is large, so that the electrical
It has a great adhesion force.Although it is very good, depending on the specifications, some parts of the board are flat.

In such a case, by creating a pattern as shown in Figure 13, the same manufacturing process of the present invention as in the M-Embodiment can be used as is to achieve the purpose.

First, the through-hole shape, pattern shape, and arrangement KSr in the case of the one shown in FIG. 14A in which the diode molded diode shown in FIG. , unnecessary parts in the column direction of both sides of the base material IO/(7A, 10B (Moth outer division-XI,
'X1ll+I D outside) only in column direction Dm
The peripheral part in the row direction that is closed by the part lja/jj
A large elliptical through hole /j, which is on a straight line across each column, is provided including each row direction dividing line.

Then, the straight circumferential portion of this through hole /j /jbt/
The first pattern/41A and the second pattern shape B are provided as each strip in series in the column direction. Then, in each substrate area portion C, the element mounting portion l and the wire bonding portion 13 face each other in the column direction, as shown in the portion CI-j-+ marked with line 5A. The image portions /3 and /3 together constitute a substrate surface pattern for each chip.

In addition, each back surface of each conductive layer portion or pattern portion lU, /3 is connected to the pole /? , /1 is not shown in FIG. 13, but may be the same as the front surface pattern.O Thereafter, as described in connection with the first embodiment.

Diode element 7) Q2 is installed in each area C.

Perform wire bonding work and attach the seal to the base material 1.
After applying it to the entire surface of 0, in the 1st row direction, use the row direction dividing line passing through the center of each through hole /S.

The column direction f is a series of first and second pattern arrangements in the row direction,
If the base material 10 is cut along the column direction dividing line that cuts off 74 tB, the conductive layer 1q on the side surface of the substrate core, /? The terminal is flat, and in this case, the terminal is on the back surface, and a square shaped one weighing 7g is provided.

In addition, in FIG. 13, there are two pounding parts/, ? for each chip, as shown by the imaginary line in the figure for the second butter 7/JIB. If formed as A, /JB.

@141 As shown in the figure, even with a three-terminal element n such as a transistor, it is possible to form a chip component B or three mini-mold transistors in which each vertical conductor, -l de..., is shaped like a thousand ryo (,11 !Both pattern parts/l
, /$B can be used for multi-terminal elements by increasing the number of divisions in the row direction, and in that case, the planar terminal pitch on both sides of the 4-plate body is standardized or treated similarly using this type of technology. pitch.

For example, if it is 1, 27-, the dual/line pin arrangement L (L) of this kind of chip type integrated circuit can be met. Of course, single in-line is also possible without using one of the patterns /l or /lIB.

Next, an example for a passive element will be described.

Again, in these examples below.

Based on the through-hole shape shown in FIG. 13, the vertical conductive hole is made into a flat surface. However, a circular small-diameter through hole may be used as shown in FIG. 13 and FIGS. 4 to 6.

15 to 17 consider resistance as element 2. FIG. 15 shows the pattern arrangement on the base material 10 before division, and the through holes /j' are lines closed only at the truncated portions #l)A and 10B on both sides of the base material, similar to the illustration in FIG. 13. It has an elliptical shape with a linear peripheral edge ISB in the direction.

Therefore, in the surface pattern shown in Figure 1H13, the mounting part l and the wire bonding part /3 are both [.

If we consider surface connection +473,13 to connect each electrode of element = to the corresponding back surface terminal.

By connecting both electrodes of a separately made resistor between the two, the chip resistor 35 can of course be obtained.
However, in this embodiment, the patterned conductive material is a resistor material 1 such as Ninogel chromium-based, aluminum-based, ruthenium-based, etc., and in each chip substrate area C, a conductive layer for connection at both ends/, ? , /J with a predetermined width,
Three resistance source pattern portions having a predetermined thickness are integrally molded into a bridging shape.

In this state, if a resistance pupil adjustment technique such as laser trimming (using a known method, it is good) is applied to all the resistance source portions 3Q on the base material 10 to obtain the desired resistance,
As shown in FIG. 16, the resistive element 22 is obtained, and after molding, it is cut along each division.
A chip resistor 3j shown in FIG. 7 is obtained as a chip component.

In the embodiments shown in the 18th and 19th figures, the coil 37 is used as the second mounting element.

To explain the finished state of the chip coil 3g shown in Fig. 19, there is a part of the coil element forming a spiral pattern. 37 J) One end 37a is integrally continuous, and the spiral central end 3b is connected to the second pattern part/7B.

Since the first pattern part /JA has an oval through hole /3A (Fig. 18) K similar to that in the previous embodiment, the planar terminal /JA on the back side can be connected to the back side through the vertical conductive layer /9. The connection is made in the central pattern part/3
B is communicated with a slightly wide planar terminal /l on the back WJ via a through hole /lB provided in this part.

Therefore, as shown in Fig. 18, in the pattern on the C1 base material IO, the pattern portion 39 along the opposite long side of the through hole/Num is essentially unnecessary, and the conductive layer portion/ 9' is also essentially unnecessary.

In view of uniformity of pattern drawing and workability, it is generally convenient to use such a pattern. In particular, the conductive layer serves as an additional additional solder wetting area for the terminal/I, so the conductive layer is less than 1. It's hard to say it's useless.

Coil element 37 Svairalno (turn.

(other conductive)--can be performed simultaneously with pattern portion formation. In addition, the inductance (direction) can be designed because there is a mathematical equation depending on the average radius of the spiral, the number of turns, and the line width.

The embodiment shown in FIGS. 20 to 24 has a capacitor element 39 mounted as an element by using the known selective etching technique as well as the known technique of depositing multiple layers on the substrate #10 together with the aspects of the present invention. It constitutes a chip component core or a chip connector/sustainer.

In the second OA and B diagrams, two substrate area portions for each chip corresponding to one column and two rows in the base material 10 are shown.
is extracted and shown. In addition, the matrix is shown laid out horizontally, but although the rows and tallies are originally relative issues, this is done in response to the previous example and the directionality of the elliptical through hole tSO. This is because of this.

That is, along the row direction peripheral edge portions tsb and c of the through hole /S waiting for the same pressure linear peripheral edge portion /kl), the base material /θ
A narrow first pattern portion 13 and a wide second pattern portion S/3B are formed on the surface of the substrate, and together they form a pattern group.

Therefore, it is sufficient to arrange these patterns on the leather in rows.

Further, the pattern /1 around the back surface through-hole may be of one type, and the opposing edges become the respective planar terminals for the substrate surface portions adjacent in the column direction.

The wide first butter/portion/jB will in the future constitute one capacitor electrode II/ of the capacitor element.

Next, after depositing or forming an insulating layer or a dielectric layer that will become a dielectric layer of a capacitor element in the future on the entire surface of the base material 10, a predetermined pattern of dielectric film occlusions is left using a selective etching technique. Specifically, the wide pattern/JB is covered, and the narrow pattern/jA is -5JII! Presentation Sacer (21st
figure).

Next, as shown in FIG. 22, the other capacitor element of the capacitor element is coated on the entire surface of the base material 10, provided that it is exposed! A metal layer 3 made of a material that is mechanically compatible with the 1111 part/JA is formed by vapor deposition, plating, or other appropriate methods, and then a photochromic layer is applied, followed by S light, development, etc., to form the required layer. Leaves a resist island on the part.

The base material 10 is etched using an appropriate etching method to form the 'dt pole layer 413 on the surface of each chip substrate area in the first pattern portion/? A to dielectric film $/I
If the resist islands are formed so as to stay on the second pattern portion 7.7B and then remove the resist islands, the second;
As shown in the figure, the inner pressure of each chip substrate area is continuous between the upper and lower ii! pole 113, 41/
, a strip-shaped capacitor 3q consisting of a galvanic layer octopus is formed.

After that, after molding the base material surface with a mold company,
By cutting out each chip along the matrix dividing lines, a chip capacitor as a chip component as shown in FIG. 24 is obtained.

Similarly, if the capacitor capacitor 1 is made of the same material, the area and dielectric potential of each electrode type are determined by the film thickness f, and these can all be precisely controlled using current technology.

Further, as shown in the chip capacitor q' shown in Fig. 25, the E section electrode 3' may be connected and fixed to one of the conductive 11 patterns 13k by mechanical welding or the like, and the dielectric film may also be a separate dielectric film. It is also possible to close the q layers.

In this case as well, it depends on whether the manufacturing method of the present invention is adopted. In other words, capacitors may be formed in the shape of strips in one row direction (for each row), molded, and then cut. Of course, since the chip component of the present invention has sufficient inventive step as a product, it may be manufactured by an individual manufacturing method. However, compared to conventional individually manufactured chip components (Fig. 1.2), many advantages can be found.

In each of the above-mentioned embodiments, the vertical conductive layer /7, which is the inner wall surface of the through hole, and the external planar terminal /7
, /l is a separate member and friend.

That is, the planar terminal is provided on the bottom of the board and is round.

However, as can be seen from FIG.
, 30 with solder or other conductive adhesive, even if the planar terminals /7, /I are not necessarily on the bottom surface, the J: lower H inner groove conductive layer /9 is attached to this planar terminal. /7
, can also serve as /l. In other words, since one-sided terminals may be used on the side of the board, the chip components according to the present invention can be made by using through-holes/! t
A planar terminal is provided on the outer surface other than the element mounting surface.

In view of the various embodiments of the present invention described above.

The main effects of the present invention can be summarized as follows.

First, if you look at it as a physical object: :) The element mounting surface and the surface on which the external planar terminals are provided are different surfaces, so there is no need to turn it over when mounting. Therefore, even if a phototransistor or a light emitting diode is selected as an element for exchanging information with nine external circuits, if a transparent molding material is used, the function can be performed without any problem, and the conventional method as shown in Figure 1.2 can be used. The conductive 4Ci-pattern as seen in chip parts is
It never becomes l.

11) In addition, in the conventional structure chip, the element mounting surface and the planar terminal are on the same side, so in order to mold the element and present 4 single planar terminals, K must exceed the 4 tastes of the molding material. Therefore, consideration must be given to positioning the planar terminal above the element; that is, the conventional structure shown in FIG.
#8 #The difficult process of forming the IC is essential and costs 1M! In the conventional structure shown in the drawings, it is necessary to connect the leads extending to the outside due to manufacturing requirements.

On the other hand, in the chip component of the present invention, in principle, it is not necessary to form irregularities by machining the substrate tips. However, since it only needs to be flat, its suitability and femininity are extremely high.

! 11) In the conventional structure, no matter how small the substrate rjH is -1, it will never be as small as the element area and each 1ilE4WJ product, and it is impossible to make the No. 9 electrode area too small. Therefore, there is a limit to miniaturization, and even more so, in the structure shown in the second figure, the manufacturing workability (at least to the outside 7) and the overhang of the I node is Tof4, but it is 1
In the present invention, such limitations are reduced to a large extent, and the packaging density can be greatly increased.

For example, if one electrode of an element is made conductive to the back side with a through hole that passes directly below the mounting surface of the element, the area can be reduced by that much. Even if you take enough area and overlap the surface element in position, it will not make any difference.

The surface pattern connecting the through hole between the element and this back electrode can be made extremely small.

Furthermore, when a one-plane terminal is formed on the side surface, that is, when the seven H direction conductive layer itself formed by the conductive layer on the inner wall of the through hole is used as a plane terminal, the peripheral area of the J@ element element area Ki is It can be maximized to the added maximum Iarri product chip.

IV) With regard to through-hole technology, the range of substrate materials for DIM is wide, and it is possible to use inexpensive ones, and we also choose compatible materials such as choosing Epoki 7 resin for the mold material and glass Evokin for the base material 10. The degree of freedom in selection increases, mechanical damage due to differences in temperature coefficients can be prevented, and cutting becomes easier.

Next, manufacturing the chip component of the present invention by the manufacturing method of the present invention further produces the following advantages.

6) First of all, the production process has been greatly simplified.

Both productivity and economy will be significantly improved. In the present invention, when mounting the tip element on the base material lo, f-, when performing the wiring work, and also.

Even in the molding process, it is possible to process a large number of elements on the base material 10 at once.

It is possible to process the base material 1O, which is a large-area component, and only needs to start dividing and cutting each chip component in the final step.

Therefore, as in the past, extremely precise and expensive equipment is required to send the microscopic substrates that have already been cut out one by one to the processing station while aligning the directions for each process. Required for each element mounting, wiring process, and molding process. You can escape from such a huge debt. It is extremely easy to handle the size of the base material/θ, and by orienting the base material/θ in a certain direction, each chip substrate area or conductive pattern etc. on the base material can be controlled by i! ; it is uniform, and τ points in a constant direction.

b) Contamination problems for elements and patterns can be largely avoided. As in the past, each small chip board that had been stocked in advance was taken out one by one, and then the elements were mounted, and the processed chips were loaded in order.
The process of rounding without sending to a station 7 can be done all at once in the same molding chamber or in each molding chamber, which also satisfies the uniformity of the rounding and machining conditions. can be done.

C) Related to II) above, there is no need at all in principle for the mechanical and sloppy molding process for the base material or substrate.

d) Since patterning/sharing between adjacent elements is easily possible, by increasing the number of chips that can be packed into the base material 70, utilization efficiency can be significantly improved.

-) In addition, the pattern design itself is very convenient, as it can essentially apply the technology and know-how of conventional printed S-boards.

In this way, the chip component and its manufacturing method of the present invention bring about many advantages even in raw materials.

It also provides the user with the advantage of greatly increasing packaging density.
It is clear that the company will make a significant contribution to this field, as it is expected that there will be a huge demand for this type of parts in the future.

[Brief explanation of the drawing]

The jlt diagram clearly shows the # of a conventional chip component and its manufacturing process, Figure 2 is a partially fragmented perspective view of another conventional chip component, and the lEa diagram is a conventional one for wiring between elements or for attaching a component bottle. 4, 5, and 6 are explanatory diagrams of each step of an embodiment of the manufacturing method of the present invention. Figure 7 is an illustration of the first embodiment of the present invention. The mold of the chip diode or mini-mold diode as a row is indicated by Mj- and is a perspective view, FIG. 8 is a sectional view taken along line A in FIG. 7, and FIG. 9 is a mini-mold as a second embodiment. Base material J suitable for three terminals and child parts of transistors, etc. ! FIG. 10 is a schematic perspective view of a three-terminal chip component such as a mini-mold transistor as a second embodiment of the present invention, and FIG. An explanatory diagram of a suitable base material surface conductive layer pattern, FIG. 12 is a schematic configuration perspective view of a six-terminal chip component as a third embodiment of the present invention, and FIG. 13 is a ll
Figure 4114 is an explanatory diagram of a through-hole V shape suitable for making the la plane and downward conductive i- into a planar shape, and is D as the fourth and fifth embodiments created based on the through-hole shape shown in Figure 13, respectively. Schematic perspective view of tip parts, No. 15
1. Figure 16 is a clear view of each step 8a for producing a chip resistor in accordance with the manufacturing method of the present invention, and Figure 16 is a schematic perspective view of the structure of a chip resistor as a sixth embodiment of the present invention.
Fig. 18 is an explanatory diagram of a base material made of rhinoceros layer putter/ which is suitable for producing a chip coil by the manufacturing method of the present invention, Fig. 19
The figure shows the schematic groove formation of a chip coil according to the seventh embodiment of the present invention. Figures 20, 21, 22, and 23 show a chip condenser fabricated based on the manufacturing method of the present invention. FIG. 24 is a schematic perspective view of the structure of a chip capacitor as an embodiment of the present invention, II! ! !
Figure I is a perspective view of a schematic configuration of a chip capacitor in which the capacitor element configuration is changed as a ninth practical example of the present invention.

Claims (1)

[Scope of Claims] (1) A leadless chip component for electric or electronic circuits, in which electrodes of a chip element arranged on a substrate and molded with a molding material are connected to planar terminals along the outer surface of the component. A substrate surface conductive layer pattern for connection with each electrode of the chip element is formed on the same substrate surface as the chip element mounting surface. The above-mentioned planar terminal is formed on a surface different from the above-mentioned chip element mounting surface in the outer surface of the above-mentioned component, and the mutual portion where the connection between the above-mentioned surface conductive pattern 1 and the above-mentioned planar terminal is to be made is formed through an inner conductive layer. A leadless chip component characterized in that the hole is connected by a vertical conductive layer formed as the inner conductive layer. (2) The IJ-dress chip component according to claim (1), wherein the planar terminal is provided on the bottom surface of the substrate. (3) The leadless chip component according to claim (1), wherein the planar terminal is provided on the side surface of the substrate, and the vertical conductive layer also serves as the planar terminal. (4) A method for manufacturing a leadless step component for electric or electronic circuits, which comprises connecting the electrodes of a chip element arranged on a substrate and molded with a molding material to a planar terminal along the outer surface of the component. , a step of collectively press-forming a conductive rm pattern on the surface of each chip component substrate, which takes the electrodes of each chip element, on the surface of the base material including the plurality of chip component substrate areas, and each of the chip components. with surface conductive layer pattern. A step of connecting the parts to be connected to a planar terminal having a surface different from the above surface with the inner conductive layer of a through hole with an inner conductive layer made on the base material, and arranging on the surface of the substrate area a chip element that connects the corresponding portions of the surface pattern; A step of molding each chip element by collectively molding the base surface. A method for manufacturing leadless chip components, comprising: dividing the base material after mode V according to predetermined divisions MA in the matrix direction to extract Taito D chip components. th> A method described in (4) above, characterized in that the step of forming a conductive pattern on the substrate surface and the step of forming a conductive pattern on the inner surface of the shear hole are performed in the same step. (6) rkJ-shaped terminals for each chip component, the range of special 1fnI requirements, characterized in that they are formed all at once on the base material screen at 5c before d division, any one of 4) - (5) Method 1 (7) Claim (4) e characterized in that the planar terminal is a part of the conductive layer on the inner surface of the striped hole.
The method described in item 1 of (s). (II) Each chip component substrate ti-surface conductor [1@butter/] has a portion that shares the surface pattern formed on the base material H in adjacent chip component substrate areas. Scope of claims +4) l (5)
, (6) I (7) J) Which is Kihoro's method.