JPS58212657A - Playback speed control device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a playback speed control device for a signal playback device for a digitally recorded disk, tape, or the like.

When recording information on a recording medium such as a disk or tape, a synchronization signal is generally added, and during playback, this synchronization signal is detected, and the playback speed is controlled by adjusting K so that the cycle of this synchronization signal is constant. There is. As an example of this, FIG. 1 shows a complete block diagram of a playback speed control circuit of a PCM disk playback device.

1 is the motor, 2 is the disk, 3 is the pickup C and below P
Let it be U. ), 4 A synchronization signal detection circuit detects a synchronization signal from among the signals picked up by the FiPU 5, and 5 is another reproduction speed detection circuit. □Here, the regeneration speed detection circuit 5 is used when the reproduction speed of the device exceeds the detection range of the synchronization signal detection circuit 4, and detects a unique signal, for example, the longest pulse, in the signal extracted by the PU 5, This is a speed detection circuit that predicts the synchronization signal period by multiplying this detection pulse width by eight times a multiple W determined by the ratio of (synchronization signal period during normal operation/longest pulse). 6 is a switching circuit, 7 is a switching control circuit, 8 is a frequency voltage conversion circuit (hereinafter referred to as fV converter), a constant current source 16,
Delay circuit 9, pulse generation circuit 10.11, integration capacitor 1
2. Switch 14.17. It is composed of a hold capacitor 16.

This is a drive circuit for a 15 motor 1.

The operation shown in FIG. 1 will be explained below using the time chart shown in FIG.

The playback speed of the signal (2) extracted from the disk 2 by the PU s is detected by the synchronization signal detection circuit 4 and the playback speed detection circuit 5 as a signal with a period corresponding to the synchronization signal and the speed, respectively.

When the playback speed is significantly different from a predetermined speed, such as during startup, the switching control circuit 7 and the switching circuit 6 input the output θ of the playback speed detection circuit 5 to the f-V converter 8.
works. The output of the switching circuit 6 is guided through the delay circuit 9, the pulse generating circuit 10, the switching circuit 17, the pulse generating circuit 11, and the switching circuit 14, and the switching circuits 17 and 14' are turned ON and 10FF, respectively. The pulse generating circuit 11 generates a short pulse (2) at the rising point A of (2), and at this time the switch circuit 14 is closed and the voltage of the capacitor 12 is applied to the capacitor 13. When the pulse [F] ends, the voltage of the capacitor 13 is held.

On the other hand, the output pulse Fi's of the pulse generating circuit 10 which has passed through the delay circuit 9 is generated at a point B, which is delayed, and the switch 17tl
-Turn on. At this time, the charge in the capacitor 12 is discharged and the voltage becomes zero. When the pulse of pulse generator 10 ends, current flows from current source 16 to capacitor 12.
It is integrated, and the voltage at ■ increases until the next pulse comes.

Next, the pulse generation circuit 11 outputs an A! The voltage of capacitor 13 and capacitor 12 is sampled and held by the pulse generated at point .

By the way, when the playback speed falls within the detection range of the synchronization signal detection circuit 4, the switching control circuit 7 drives the switching circuit 6 to switch the speed signal to the output @ side of the synchronization signal detection circuit 4, and based on the synchronization signal. Performs speed control.

The signal taken out by the PU 3 from the I-disk 2, which has been set to the playback speed of 1 centimeter in this manner, is input to the digital processing circuit 30 and decoded as audio data.

If there are many errors, such as when a part of the signal extracted by the PU 5 deteriorates significantly or when the signal is interrupted for a predetermined period of time, a click sound etc. will be generated in the reproduced sound, so the error detection circuit 63 When it is detected that the number of errors has exceeded a predetermined value, the muting circuit 62 is turned on to perform muting. By the way, if the error detection circuit 33 does not generate a mute signal even though the signal is lost due to a scratch or the like, and the damage is such that the audio is not interrupted, the switching control circuit 7 detects the synchronization signal detection circuit 4. It may be detected that all synchronization signals cannot be detected, and the circuit may switch to the playback speed detection circuit 5 side.

Once switched to the playback speed detection circuit 5 side, the accuracy of speed detection is lower than that of rotation control using a synchronization signal, so most of the signals obtained will be errors, and this will cause a meeting to take place.

As a result, the synchronization signal was lost for a certain period of time due to a small scratch, but the rotation of the motor was not significantly disturbed.
Audio may be interrupted due to switching of motor control signals.

The purpose of the present invention is to eliminate the drawbacks of the conventional mute system by generating a control signal that causes the switching circuit to operate only in the case of a real error such as deterioration or loss of data retrieved by the PU for a predetermined period of time. An object of the present invention is to provide a playback speed detection device equipped with a circuit.

Therefore, in the present invention, when we take the logical product of the muting signal and the switching control circuit, we find that muting is O.
The reason is that switching is possible only when the voltage reaches N.

FIG. 3 shows an embodiment according to the present invention. In FIG. 3, the same symbols as in FIG. 1 have the same functions. Here 31 is A
It is an ND gate.

The operation of the embodiment will be explained below using the figures. P.U.
As explained above, the signal i picked up in Section 3 is decoded as audio data by the digital processing circuit 30. If the playback signal is lost due to a scratch on the disc 2, the synchronization signal cannot be detected, and the switching control circuit 7 is set to "Lo".
w −j High level and attempts to switch to the playback speed detection circuit side 5, which has a wider detection range.

However, when the scratches are small and no audio meetings are performed, the number of errors within a predetermined period of time is small, and the output of the error detection circuit 33 is "Low" level IT, the output of the AND gate 31 does not change, and the switching circuit 6 also It remains connected to the synchronization signal detection side 4.

After passing through the scratched part, the speech period signal detection circuit 4 is activated again.
starts to detect the synchronization signal, and the switching control circuit 7
The output changes to "Low" level.

As explained above, if the rotation of the motor is not greatly disturbed by small scratches etc. and the number of errors is small, even if the synchronization signal is no longer detected, the switching circuit 6 remains connected to the synchronization signal detection circuit 4 side, and the motor Continue to control the rotation speed of 3.

If the scratches are large and the synchronization signal is lost and the playback speed deviates from the target value, the number of errors will increase and the output of the error detection circuit 33 will become "High" and the AND gate 31 will be turned on to control switching. The output of the circuit 7 activates the switching circuit 6, which switches to the playback speed detection circuit 5, and controls the speed so that it reaches the target value.

FIG. 4 shows an example in which the present invention is implemented in a tape playback device. In FIG. 4, the same symbols as in FIG. 3 have the same functions. Here, 40 is a head for reading signals from the tape, 41 is directly connected to the motor 3, and is a capstan for running the tape;
2 is a tape on which signals are recorded.

The capstan 41 rotates, causing the tape 42 to run, and the head 40 reads out the signal.

After speed detection, the read signal is converted to speed k by fV converter 8.
It is converted into a voltage proportional to , which is fed back to the motor 3 and controlled to maintain a constant speed.

The signal is input to the digital processing circuit 30 and decoded as audio data. As explained earlier, in this case as well, the input of the f-V converter 8 remains connected to the synchronization signal detection circuit 4 until the number of errors within a predetermined time exceeds a predetermined value and matching occurs. Stabilizes operation by preventing the servo system from switching easily due to small scratches f
It was measured.

As described above, according to the present invention, by using the meeting signal as the gate signal of the switching control signal,
It is possible to obtain a playback speed control circuit equipped with a meet circuit that does not interrupt the sound due to switching of the motor control signal even though the motor rotation is not greatly disturbed and the signal can be played back.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a conventional circuit diagram, FIG. 2 is a time chart diagram showing the operation of FIG. 1, and FIG. 3 is a circuit diagram of an embodiment of the playback speed control device according to the present invention. FIG. 4 is a circuit diagram of another embodiment of the present invention. 1...Motor 2...Disc 3...
Pickup 4... Synchronous signal detection circuit 5...
Playback speed detection circuit 6...Switching circuit 7...Switching control circuit 8...F-V converter 30...Digital processing circuit 3l-AND circuit 33...Error detection circuit 40...Hera) "42...f-7"
Figure 3 Figure 4

Claims (1)

[Claims] In a signal reproducing apparatus that reads a digitally recorded signal from a recording medium with a signal reading apparatus and reproduces the recorded signal with a signal processing circuit, a plurality of speeds are provided for outputting a speed detection signal corresponding to the reproduction speed from the read recorded signal. A mute function that supplies each output of the control signal generator to a switching device, and mutes the switching device to mute the output of the speed switching control signal generator and the reproduced signal output when the quality of the signal is degraded or the signal stops for a predetermined period or more. A playback speed control device characterized in that the recording medium is switched by an AND signal output from a control signal generator, and the signal is returned to the stone drive device.