JPS5821955A - Emergency controlling system - Google Patents

Abstract

PURPOSE:To clear the flag of the restart working level and to assure the restart working control, by monitoring the normality of the software of a program for a certain period by the program of a CPU after a system is restarted and resetting an urgent monitoring circuit after confirming the above-mentioned normality. CONSTITUTION:The CPU100 and 101 are doubled, and the communication service given by the doubled CPU100 and 101 is restarted under the control of an urgent control circuit 200 in case a grave fault is caused to unable a continuous call process. An urgent control circuit 300 is connected to the CPU100 and 101 as well as to the circuit 200. When a restart factor is detected by an urgent control start factor detecting circuit of the circuit 300, a restart instruction is given to the circuit 200. Then the normality of the software is monitored for a certain period by the programs of the CPU100 and 101 after the restarting. The counter and the flag of the circuit 300 are reset after the above-mentioned normality is confirmed by said counter and flag. Thus the control is assured for the restart working.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an emergency control system in an electronic exchange equipped with an emergency control monitoring circuit that monitors the normality of software due to start-up and restart operations of an emergency circuit.

For example, phase 1 is the restart level for electronic exchanges.
Resume (The emergency control 1M circuit (hereinafter referred to as the EM circuit) is automatically activated and all calls are cleared, but the O system status such as the congestion 1 line closure when a failure occurs remains. ), Phase 2 Re-II (same as Phase I restart, but the system status is also cleared) and 7Aze 3 restart (EM circuit does not operate automatically, also called system down). , quadratic, phase 1
Then, in phase 2 re-activation, the IMAwA path is activated to restart the system, the communication service is restarted again, and emergency control is carried out within a certain period (for example, one day).
6) The number of activations is less than or equal to 15 (hereinafter referred to as EM).
11 or less), the counted number of times is cleared, and if the number exceeds the fixed number of 9 KM, restart Phase 1 and restart Phase 2 (11 KmI), the counted number of times is cleared. . Therefore, the normality of the software after the system restart operation is not confirmed, and there is a risk that the ΣMAIiM path will be activated many times over a long period of time due to a latent software bug. The drawback was that the timing of reopening was not clear.

The present invention starts a monitoring timer when the EMA is activated, monitors the normality of the software for a certain period of time using a program that controls the central processing unit, and when the normality is confirmed, starts the EMAIJ try counter and resumes operation. If the normality of the software cannot be confirmed after clearing the flag indicating the level of the
III! If an impossible failure occurs, nothing will be cleared, and the EM trial counter will continue to count, and when the value reaches a certain value, the phase 1 will be restarted and the phase 2 will be restarted. Or by a method of transitioning from Phase 2 re-■ to Phase 3 restart), the above drawbacks can be resolved and system restart control can be ensured. The purpose of this invention is to provide an emergency control method that performs the following operations.

That is, the present invention has a redundant central processing unit, and has an emergency control system 1 which causes the redundant central processing unit to restart the overconfidence service when one line of call processing cannot be completed and another serious failure occurs. circuit and an emergency control microcircuit for monitoring and controlling the operation of the electronic exchange, or an electronic exchange emergency control circuit, wherein multiple levels of restart operation are defined according to the number of activations of the emergency control circuit. A control method,
The emergency control circuit 1 includes an emergency control activation factor detection circuit that generates a signal each time a factor that should activate the emergency control circuit occurs in the system, and a signal generation circuit from the detection circuit. means for displaying a plurality of flags provided corresponding to each of the plurality of restart operation levels; Equipped with an emergency control activation circuit that activates the emergency control circuit according to the display state, and a microscopic timer that records the required time predetermined by the system after the emergency control circuit is overworked, the above-mentioned monitoring tie! - is configured to clear all of the above-mentioned retry run 11 monitoring timer and the above-mentioned flag indicating the 7-Ace resumption state after the timeout and death of the above-mentioned central processing unit (in response to a return command from the program controlling the central processing unit). It is something.

Below, the present invention will be explained based on the embodiments shown in the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the same figure, dual central processing units 10G and 101 are connected to K via signal lines 110 and 111, respectively.
It is connected to the MM monitoring circuit 300.

The IMA II visual circuit 30G has two central controllers Zoo
The KMA 14M1120G must be operated in either of If there is no activation signal, the KM monitoring circuit 300 outputs an EM activation signal to the signal line 120K according to the number of KM activations.
While activating the AI circuit 200, in order to activate an alarm according to the current system status 11, the alarm activation signal is a signal @ 14 that is connected to the EM monitoring circuit 1 for 300 km.
1, 142 or 143), then phase I re-N, phase 2 restarted.

Indicates phase 3 restart.

When the IMAH circuit 200 receives the KM activation signal,
Depending on the signal, a phase 1 restart or phase 2 restart signal is sent to the center via the signal line 130 or 131.
Control device 10G or 10IK is transmitted.

11E! II is a block diagram showing the configuration of the KM monitoring system 300. In the figure, the EMA activation factor detection circuit 310 connects the signal line 110 and IIIKm! When the KM activation factor is detected, the retry counter 3
The KM activation factors that send the 20 KN M activation request signal are roughly divided into two. One is a failure of the central processing system, and the other is a case where the normality of the software operation was not confirmed by starting the gM system.
The count is incremented by one each time the program activation factor detection m1s310 signal is received. And Retry Own 132
0 is an overflow (for example, if the counter is 3 bits, EM activation requests occur 8 times within a certain period of time)
When this happens, flag a331#i4 is set. The EMA activation circuit 340 receives the 'EM activation request signal and the 7 lag a 33
Depending on the value 10, a signal indicating whether to activate the phase I re-111 EM or phase 2 restart EM is received, and the EM circuit 200 is operated in accordance with the signal.

When the IMAO path 200 is started, the monitoring timer 380 is started as soon as the system restarts.
The central processing unit itself checks whether the central processing system software is operating correctly for a certain period of time, and if the normality of the software is confirmed, the reset circuit 370 receives a reset command and sets a retry own J 320 flag. a
331 and set the timer SSO. If the reset command is not received, after a timeout, the value of retry own-320 is increased. If KI during this confirmation period
Tori Trikaran J 320 that receives Mmu activation request request
The 0 value is raised, the supervisory tie-v-380 is reset, and the 0 value is again multiplied by II+, causing a similar O operation.

The phase I re-sign is passed through the delay circuit 360 to the nine EMAs.
The phase 2 restart signal is generated by the input ND circuit 351 from the AND of the flag 1331 and the inverted value of the flag 1331 and the inverted value of the 7lag b3320, and the phase 2 restart signal is generated by the KM5 activation request signal passed through the delay circuit 360, the flag turtle 331 $P and Flag b is generated by the ANDI circuit 352 from the inverted value of 3B2.

Delay [191360 Fis When there is a vM activation request signal, the retry counter 320. Flag turtle 331 and flag b 332 react thereto and issue a sufficient delay for the operation to be completed, as well as activate the respective alarms of the phase 1 restart signal and phase 2 restart signal at that time. Signal lines 141 and 142K are sent. Phase 3 re-II (system down) is activated when the flag b332 is set and the signal line 143 is turned on. The flag b332 is set when the flag a331 is set and the retry counter 3
20 overflows, this is done by the AND circuit 353.

As explained above, in the present invention, after the restart operation of one system,
The central processing unit program monitors the software's normality for a certain period of time, and if it is confirmed, the EM monitoring 1111
By issuing a reset command and clearing the KM multitry count and the restart operation level flag, the normality of the communication service due to the restart operation is sufficiently guaranteed, and the restart operation control can be reliably performed. be.

[Brief explanation of the drawing]

FIG. 2 is a block diagram showing an example of a central processing system including a BM monitoring circuit which constitutes the present invention. 100, 101...Central processing unit 20G...Emergency control (IMA) circuit 300-...Emergency control (EMA) monitoring circuit 310...Emergency flill
lCEM) Activation factor detection circuit 320--Retry counter 331--Flag a332--Flag b 34G--Emergency control (EMA) activation circuit 3pl, 3
52.3! $3-A N D 1 circuit 360-)l
Low circuit 37G--Reset circuit 380--Monitoring timer applicant NEC Corporation Figure 1

Claims (1)

[Scope of Claims] An emergency control circuit having a redundant central processing unit and causing the redundant central processing unit to re-establish communication services when a serious failure occurs that prevents call processing from continuing. and an emergency control monitoring circuit to monitor and control the operation of the circuit, and an electronic exchange taO* in which a plurality of levels of restart operation are defined depending on the number of activations of the emergency circuit. With the sudden control force control method, the above emergency control monitoring circuit should start the emergency control circuit.
No signal is generated to 11 which detects that the m cause has occurred in the system. a retry counter for counting the number of times a signal is generated from the detection circuit; means for displaying a plurality of flags provided corresponding to each of the plurality of restart operation levels; An emergency control activation circuit that receives an output signal from the emergency control activation factor detection circuit and activates the emergency control circuit according to the display state of the flag, and a time predetermined by the system after activation of the emergency control circuit. After the monitoring timer times out, the retry counter, the watch timer, and the flag indicating the phase restart status are all reset by a reset command from the program that controls the central processing unit. An emergency Wi control method characterized in that it is configured so that it is completed immediately.