JPS5824193A - Electronic musical instrument - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] The present invention relates to an electronic musical instrument that plays automatic performance sounds in synchronization with key presses on a keyboard, and in particular, when a key that is out of the normal performance is pressed, it is possible to use a genuine key suitable for the performance. The present invention relates to a device in which the performance of the automatic performance sound is stopped until the button is pressed.

In general, automatic performance devices for electronic musical instruments include those that automatically play melody sounds or other musical tones based on reading sheet music data, those that automatically play bass sounds and chord sounds, those that automatically play arpeggio sounds, and those that automatically play rhythm sounds. There are some that play automatically, and others that combine these as appropriate, but in all of them, once you set a tempo and start, this initial tempo is maintained until the end and the automatic performance is performed.

In an electronic musical instrument equipped with such an automatic performance device, when keys are pressed on a single keyboard in synchronization with automatic performance from the automatic performance device, it is preferable that the key press timing and the progress of the automatic performance coincide. For example, consider a case where you perform manual performance on the keyboard while the automatic accompaniment progresses.
If the key press timing is earlier than the progress of the automatic accompaniment, the automatic accompaniment performance will maintain a constant tempo regardless of the key press, so if the next key press timing has an appropriate note length interval, the automatic accompaniment performance will continue. The progression from the beginning will remain as is, and if the timing of the next key press is set to match the automatic accompaniment performance, the interval between key presses will become longer, making it impossible to obtain an appropriate note length. On the other hand, if the key press timing is late compared to the automatic accompaniment performance, if the next key press timing has an appropriate note length interval, the delay from the automatic accompaniment performance will remain, and the next key press timing will be delayed. If you match it to automatic accompaniment performance, the interval between key presses will become shorter, and you will also not be able to obtain the appropriate note length. In this case, the automatic accompaniment performance will continue regardless of whether or not a genuine key suitable for the performance is pressed, so if there is a mistouch, especially for beginners, it may be difficult to keep up with the automatic accompaniment performance. be.

Furthermore, if we consider the case where keys are pressed on a keyboard in accordance with the progress of an automatic melody sound performance for practicing melody sound performance, etc., in this case too, conventional devices check whether a genuine key suitable for the performance has been pressed. Regardless of the situation, the automatic melody tone performance would proceed automatically, so even if an attempt was made to press the genuine key again, it would not work.

This invention was made in view of the above-mentioned points, and if the key pressed on the keyboard deviates from the normal performance, the progress of automatic performance is stopped until a genuine key suitable for the performance is pressed. The purpose of the present invention is to provide an electronic musical instrument that has the following features.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a melody tone automatic performance function that reads recorded data on a magnetic tape 1a formed on a musical score 1 with a musical score data reading device 2, and automatically plays melody tones based on this read data, as well as chord tones, bass tones, etc. This embodiment shows an embodiment in which the present invention is applied to an electronic musical instrument equipped with an automatic accompaniment tone performance function for automatically playing accompaniment tones and an automatic rhythm tone performance function for automatically playing rhythm tones. However, in this embodiment, the automatic performance of the melody sound based on reading the score data is executed for melody performance practice, and is used to automatically play the melody sound at a low volume and to display the key to be pressed next. It will be done. That is, in this embodiment, the automatic performance of the melody tone is always performed and displayed one note earlier.

The output of a musical score data reading device 2 for reading data recorded on a magnetic tape 1a formed on a musical score 1 is applied to a data memory 3, and a data format corresponding to the read data is selected. An example of this data format is shown in Table 1.

In Table 1, each data D+ (+=1...n) consists of pitch data TLI and note length data TL2, and pitch data TL1 is, for example, a 4-bit note code N indicating a note.
The code is composed of a total of 7 bits of data including C and a 3-pit octave code oC indicating an octave, and the note length data is composed of, for example, 8 bits of data. An example of note length data is shown in Table 2.

Table 2 Also, a rest is represented by setting all bits of pitch data to "°O", and the end Dn indicating the end of data sets all the pits of pitch data TLI and note length data TL2 to 1. ”.

Reading of each data DI from the data memory 3 is performed by the address counter 4. This address counter 4
First, when turning on the power, the start/stop control circuit 5
It is reset by the output of the 7 lip 70 knob 51. In other words, 7 trips 70 of the start/stop control circuit 5
An initial clear signal 'I-C generated when the power is turned on is applied to the set terminal S of the knob 51 via an OR circuit ORI, thereby setting the flip-flop 51 and initially clearing the address counter 4. Further, the output of the 7-lip flop 51 of the start/stop control circuit 5 is connected to the disable terminal D of the data memory 3.
1. S, making the data memory 3 inoperable.

Next, when the start set switch 52 of the start/stop control circuit 5 is turned on, the output of the start set switch 52 is differentiated by the differentiating circuit 53 and then applied to the reset terminal R of the flip 70 knob 51 to reset the flip flop 51. do. As a result, the reset of the address counter 4 is canceled and the data memory 3 becomes operational.

Further, the differential output (one pulse) of the differentiating circuit 53 is applied to the reset terminal R of the flip 70 knob 54 via the OR circuit OR2, resets the flip 70 knob 54, and is sent out as a start set signal SS. The output Q of the flip 70 knob 54 is used as a play signal PL, as will be described later. In this case, the start set signal 5S (one pulse) is generated, but the play signal PL is 11.
0 remains as II. Further, the output of the differentiating circuit 53 is applied to the clock terminal CK of the counter 4 as an address clock signal ACK via the OR circuit OR3, advances the address counter 4 by one switch, and outputs the first data D1 from the data memory 3, that is, the first sound. Pitch data related to TL1
and read out the note length data TL'2. The pitch data TLI and note length data TL2 read from the data memory 3 are applied to the latch circuit 6. The output of the OR circuit 3 (address clock signal ACK) described above is applied to the strobe terminal S of the latch circuit 6 via a delay circuit 7. TLI and note length data TL
Latch 2. Among the data latched in the latch circuit 6, the pitch data TL1 is added to the rest detection circuit 8, the key display control circuit 91 of the melody sound forming section 9, and the automatic performance melody sound forming circuit 92, and the note length data TL2 is latched. added to circuit 10. However, the latch circuit 10 is
The output of the OR circuit OR3 is directly connected to the strobe terminal S (
(without delay), the note length data TL2 regarding the first note is not latched. The rest detection circuit 8 is for detecting rests, and as mentioned above, rests are expressed by setting all bits of pitch data TL1 to O'', so this can be used to detect rests. is detected, and a rest detection signal RD is generated.

The key display control circuit 91 of the melody sound forming section 9 is for controlling the display of the key corresponding to the added pitch data TL1, and becomes operational when the key display select switch 93 is turned on. A key display signal for displaying the key corresponding to the pitch data TL1 is sent to the upper keyboard 94. Upper t11. The panel 94 is provided with display lamps in which '-h' corresponds to each key 3, l'r-'7, 4 and 1 display lamps are shown in detail, and the corresponding display is displayed according to the key display signal from the key display control circuit 91. Turn on the lamp. Note that when the key display select switch 93 is off, the key display control circuit 91 is inactive, and the key display for the 1st key 1194 is not performed.

Further, the automatic performance melody sound forming circuit 92 is for forming a melody sound corresponding to the added pitch data TL1. The automatic performance melody sound forming circuit 92 becomes operational when the melody sound automatic performance selection switch 95 is turned on, forms a musical sound signal corresponding to the melody sound indicated by the added pitch data, and sends this to the sound system 1.
In addition to 1, make it sound as a melody sound. Note that when the melody sound automatic performance selection switch 95 is off, the automatic performance melody sound forming circuit 92 is inactive, so that no melody sound is generated by automatic performance.

That is, first, under the condition that the key display select switch 93 is on, the key of the first note to be played (the key to be pressed first in II) is displayed by the display lamp provided on the key, and the melody tone is automatically played. The first note of the performance (the note to be produced first) is produced under the condition that the select switch 95 is on.

Note that the sound produced by the automatic performance melody sound forming circuit 92 is "'pronounced", so normally the melody sound automatic performance selection switch 95 should be turned off or the volume for adjusting the volume of the automatic melody sound ( (not shown) before use.

The following description will be made assuming that the melody tone automatic performance selection switch 95 is OFF.

In this state, when a key on the upper keyboard 94 whose display lamp is lit is pressed, this pressed key is detected by the key switch circuit 96, and a key code KC (bit note) indicating this pressed key is sent from the key switch circuit 96. (consisting of code NO and 3-bit octave code OC) is output. This key code KC is applied to the melody sound forming circuit 97. The melody sound forming circuit 97 uses this key code K.
A musical tone signal corresponding to the melody tone indicated by C is formed, and this signal is added to a sound system 11 to be generated as a melody tone.

In addition, the key code K output from the key switch circuit 96
C is applied to eight inputs of the comparator circuit 12.

The comparison circuit 12 has pitch data TL1 of the data latched in the latch 6 added to the input to the input, and pitch data TL1 (indicating the note to be pressed) added to the input to the input B. When the added key codes KC (indicating the pressed sound) match (A=8), a minus multiple sign is output. This minus number multiple is added to the AND circuit 1. The AND circuit A1 receives a key-on signal KON (°1'' when the key is pressed) output from the other input key switch circuit 96.
and when the key is released, the signal becomes 0″-) is sent to the differentiator circuit 1.
A signal differentiated by 3 is added, and on the condition that a key whose display lamp is lit is pressed, a pulse (key pressed - several times the number) KEQ synchronized with the pressing of the key is output. This key depression multiple number KEQ is applied to the fast-forward stop control circuit 15 via the select switch 14, and is also applied to the set terminal S of the 7-lip 70 knob 54 of the start-stop control circuit 5 and the AND circuit A2. Note that when the select switch 14 is switched to the opposite side from that shown in the figure, the signal KEQ is generated no matter what key is pressed on the keyboard. The following description will be made assuming that the select switch 14 is not switched as shown in the figure.

The fast-forward stop control circuit 15 does not operate in response to the addition of the above-mentioned -first key press-several number KEQ. However, the flip-flop 70 knob 54 of the start-stop control circuit 5 has been reset, and the play signal PL output from the flip-flop 54 is added to the AND circuit Δ via the delay flip-flop DF1 and the inverter IN1.
2 is operable, so press the key - several times 8 K E
Q is applied to OR circuits OR3 and OR4 via this AND circuit A2. Therefore, the address clock signal ACK is output from the output of the OR circuit OR3, and the address counter is advanced by one step. The output of the OR circuit OR4 is also applied to the tempo control circuit 16 as a key-on timing signal KOT.

This key timing signal KOT is used in the tempo control circuit 16 to control the generated tempo pulse TP, as will be described later.

In addition, the flip-flop 54 is a single-sale opening key pressed - several times number K
It is set by EQ, and the play signal PL rises to "1", so the signal applied to the AND circuit A2 via the delay flip-flop DF1 and the inverter IN1 becomes O" with a delay of one clock time from the rise of the play signal, and the AND circuit Δ2 becomes inoperative and AND circuit A2
Passing of subsequent key press-several number KEQ is prohibited.

Also, since the output of the OR circuit OR3 is applied to the strobe terminal of the latch circuit 10, the latch circuit 10 has the latch 6.
The note length data TL2 related to the first note latched in is latched.

-The address counter 4 is advanced by one step by the first key press-multiply KEQ, and the data memory 3 is advanced by one step.
data D2 (pitch data TL1,
The code length data TL2) is read out, and this data D2 is latched into the latch circuit 6 by a signal obtained by delaying the output of the OR circuit OR3 by the delay circuit 7. Of the data latched in the latch circuit 6, the pitch data TLI is applied to a rest detection circuit and a melody sound formation circuit 9, and is used to detect rests and to display indicator lamps placed on the key of the next note to be sounded. Controls lighting. These controls are similar to those described above.

Also, a play signal PL generated from the start/stop control circuit 5 is applied to the tempo control circuit 16. The tempo control circuit 16 forms the tempo pulse TP that determines the tempo of automatic performance in this embodiment, and the detailed configuration will be explained later, but in the initial state, the play signal PL is
A preset initial tempo pulse is output on the condition that . This tempo pulse TP is applied to the clock terminal CK of the rhythm counter 17 via an AND circuit A3 and an OR circuit OR5.

The rhythm counter 17 counts the tempo pulses TP and controls the progress of automatic accompaniment tone performance, which will be explained below. The rhythm counter 17 is configured to be initially set by the output of the flip 70 knob 19, which is set by a signal obtained by differentiating the play signal PL described above by the differentiating circuit 18. - Also, the stop switch 2o is for stopping the automatic performance of accompaniment sounds, and by turning on the stop switch 20, the flip-flop 19 is reset and the rhythm counter 17 is made inactive.

The output of the rhythm counter 17 is applied to the rhythm pattern generation circuit 211 of the accompaniment sound forming section 21. The rhythm pattern generation circuit 211 stores a predetermined performance pattern using the output of the rhythm counter 17 as an address signal, and has an eid-only memory, and sequentially generates pattern pulses based on this performance pattern in response to the output of the rhythm counter 17. do. Pattern pulses generated from the rhythm pattern generation circuit 211 are applied to an accompaniment sound formation circuit 212 and a rhythm sound formation circuit 213.

The accompaniment sound forming circuit 212 detects the pressed key of the lower keyboard 217C, detects the output of the key switch circuit 214 which outputs key information indicating this key, and detects the pressed key of the pedal keyboard 215, and outputs key information indicating this key. It receives the output of the key switch circuit 216 that outputs key information indicating the key information, and generates musical tones corresponding to accompaniment tones such as chord tones, bass tones, and albejo tones based on the key information and pattern pulses sequentially output from the rhythm pattern generation circuit 211. form a signal.

Further, the rhythm sound forming circuit 213 opens and closes a compound rhythm sound source based on the pattern pulses generated from the rhythm pattern generating circuit 211, and forms a musical sound signal corresponding to the rhythm sound.

Note that there are various well-known devices that form accompaniment sounds such as chord tones, bass tones, and arpeggi B tones based on key information and pattern pulses from the lower keyboard and pedal keyboard, and devices that form rhythm tones based on pattern pulses. A detailed description of the configuration will be omitted in this specification.

The musical tone signal representing the accompaniment tone thus formed by the accompaniment tone forming section 21 is added by 1 to the sound system 11, and is emitted as a musical tone.

In this way, the indicator lamp disposed on the key corresponding to the second note in the upper keyboard 94 of the melody sound forming section 9 lights up, and the indicator lamp of the upper keyboard 94 lights up when automatic accompaniment tone play has started. When the key being pressed is pressed, a match signal is generated from the comparator circuit 12, the AND circuit A1 becomes operational, and the pressed-several @KEQ signal is applied to the fast-forward stop control circuit 15 via the select switch 14.

The fast forward stop IIJ8 circuit 15 determines whether the timing of pressing a key on the upper keyboard 94 is early or late based on the note length data T L'2 latched by the latch circuit 10, and if it is early, outputs a fast forward signal FF, and when it is slow. If so, a stop signal ST is output. This fast forward signal FF is applied to the AND circuit A4, inverted by the inverter IN2, and applied to the AND circuit.

As a result, the AND circuit A3 becomes inoperable, but the AND circuit A4 becomes operable, and the high-speed clock pulse φ is passed through the AND circuit A4 and the OR circuit OR5 to the tempo pulse T.
Output as P. Therefore, the automatic performance progresses rapidly, and the progress of the automatic performance is made to coincide with the key press timing. Further, the stop signal ST is inverted by an inverter IN3 and applied to AND circuits A4 and A3. As a result, the AND circuits A4 and A3 become inactive, so the tempo pulse output from the OR circuit OR5 is stopped, and the progress of the automatic performance is stopped. As will be clear from the explanation that will be given later, this stop 1- continues until a key is pressed, so that the progress of the automatic performance and the timing of the key press can be made to coincide.

A detailed configuration example of the fast forward stop control circuit 15 is shown in FIG. In FIG. 2, the counter 151 has the output of the OR circuit OR3 (FIG. 1) applied to the reset terminal R, and the tempo pulse TP applied to the clock terminal GK. , the tempo pulse TP is reset in synchronization with the key press timing of the first note) and thereafter the tempo pulse TP is counted.

The comparison circuit 152 has the output of the counter 151 at the B input,
The output of the latch circuit 10 (FIG. 1) is applied to the input to the . In this case, the information latched in the latch circuit 10 is the note length data TL2 regarding the first note, as is clear from the above description. The comparator circuit 152 compares the code length data TL2 applied to the six inputs with the count value of the counter 151. If A>B, it outputs a signal '1°' to the line 153, and if A=8, it outputs the signal '1°' to the line 154. Signal II I
Enter II.

The key press timing for the second note may be earlier, coincident, or later depending on the relationship with the note length DTL2.The operation in each case will be explained below.1) When the key press timing is early If the key timing is earlier than the code length data TL2 latched in the latch circuit 10, the key press-number multiple KEQ occurs before the count value of the counter 151 reaches the code length data TL2. Therefore, at the timing when the key press-several number KEQ occurs, the comparison circuit 152 outputs line 1.
53, a signal 11111 is generated, and the key pressed - several times the number KE
An AND condition that takes the AND condition of the signal on the Q1 line 153 and the signal obtained by inverting the rest detection signal RD from the rest detection circuit 8 (FIG. 1) by the inverter IN4 (in this case, the rest detection signal RD is set to 0''). The output of IA5 becomes 1", and the output of this AND circuit △5 is applied to the set terminal S of flip-flop 155, so flip 70
5 is set. The output Q of the flip-flop 155 is sent out as a fast-forward signal FF, and as described above, enables the AND circuit A4 (FIG. 1) to rapidly advance the automatic performance.

Further, the output of the flip-flop 155 is applied to the AND circuit via the delay flip-flop DF2.

The AND circuit A6 connects the other input to the above-mentioned inverter IN4.
(a signal obtained by inverting the rest detection signal RD) and the signal on line 154 outputted from the comparator circuit 152 are differentiated by a differentiating circuit 156, and a code length-number multiple KEQ is added thereto. Therefore, A=B is established in the comparator circuit 152, and the AND condition is established at the time when the code length signal minus the multiple number LEQ is generated, and a signal "1" (pulse signal) is output. This signal is applied to the OR circuit OR3 (FIG. 1) via the OR circuit OR6, and applied to the clock terminal CK of the address counter 4 as the address clock signal ACK, thereby advancing the address counter 4 by one step. By the way, in this case, since the counter 151 is advanced by the high-speed clock φ, it instantly reaches the note length data TL2, and the comparator circuit 1
At 52, A=B holds true. Therefore, the AND condition of the AND circuit 6 is established almost at the same time as the key press - several times the number KEQ, and the address counter 4 reaches 1 almost at the same time as the key press - several times the number KEQ.
You can proceed step by step. In addition, the output of 6 to the AND circuit, the output of the OR circuit OR7 which takes the OR condition of the scoot set signal @SS, and the initial clear signal IC are added to the reset terminal R of the flip 70 knob 155 that outputs the fast forward signal FF. In this case, the flip-flop 155 is reset by the output of 0 to the AND circuit, and the fast-forward signal FF becomes O''.

In other words, if the key press timing is earlier than the note length data TL2 latched in the latch circuit 10, the counter 1
The automatic performance is rapidly advanced until the count value of 51 matches the note length data TL2, and the automatic performance progress is made to coincide with the key press timing.

2) When the key press timings match If the key press timings match the note length data TL2 latched in the latch circuit 10, the key press timing - number multiple number KEQ
At the same time, A=B holds true in comparator circuit 152 and signal II 111 is generated on line 154. This signal path 1°
' is differentiated by the differentiating circuit 156, and the sign length minus the number multiple L E
It is added as Q to AND circuit A7. AND circuit A7
, the output of the inverter IN4 which is an inversion of the rest detection signal RD and the key press-number multiple KEQ are added to other inputs. Therefore, the AND condition of AND circuit A7 is satisfied,
The signal 11111 (pulse signal) is passed through the OR circuit OR6 to the OR circuit 0. Add to R3. As a result, the OR circuit OR3
An address clock signal ACK is generated at the input of the address counter 4.
is advanced one step. That is, if the key press timing matches the note length data TL2 latched in the latch circuit 10, the address counter 4 is advanced to the next step without applying any control to the tempo pulse TP.

3) When the key press timing is late If the key press timing is late with respect to the note length data TL2 latched in the latch circuit 10, or when the correct key press is delayed due to a mistouch, the key press - several times KEQ The count value of the counter 151 is equal to the note length data T before
When L2 is reached, the comparison circuit 152 establishes A=B, and the differentiation circuit 156 generates the code length minus the number multiple LEQ. This mark length signal LEQ is sent to the AND circuit 8, and the other input is inverter T.
The output signal of N4 and the signal obtained by inverting the output of AND circuit A7 by inverter INS are added. In this case, the rest detection signal RD is °l Q II, and the output of AND circuit A7 is O'', so the AND circuit is applied. The AND condition in step 8 is satisfied, and the signal "1" is output. The output of 8 to this AND circuit is the inverted output Q of flip-flop 155 to the other input.
(in this case, "1") is applied to the set terminal S of the flip-flop 157 via the AND circuit A9. As a result, the Noritsu flop 157 is set. The output Q of this flip 70 knob 157 is the stop signal S
T, and as mentioned above, the AND circuit Δ3, A
4 (FIG. 1), and the progress of automatic performance is temporarily stopped.

Further, the output Q of the flip-flop 157 is applied to the AND circuit Δ10 via the delay flip-flop DF3. The AND circuit A10 has the output of the inverter IN4 and the key press-number multiple number KEQ added to the input of the equation. Therefore, AND circuit A10 satisfies the AND condition at the timing of key press-several number KEQ, and passes the signal 1111M pulse signal> through OR circuit OR6 to OR circuit 0R3 (first
In addition to the above, the address counter 4 is advanced by one step by generating the address clock signal ACK. The reset terminal R of the flip 70 knob 157 that outputs the stop signal ST is connected with the output of the AND circuit -810, the output of the OR circuit OR8 which takes the OR condition of the start set signal SS and the initial clear signal IC. In this case, 7 is determined by the output of AND circuit Δ10.
The lip flop 156 is reset and the stop signal @ST becomes "0".

In other words, if the key press timing is later than the note length data TL2 latched in the latch circuit 10, the progress of automatic performance is paused until the key press occurs after the key press timing matches the note length data TL2. to match the progress of automatic performance with the key press timing.

In the above operation description, it is assumed that the rest detection signal RD output from the rest detection circuit 8 is 0'', but if the rest detection signal RD is 1'', that is, the next note to be pressed is a rest. If it is a mark, the key will not be pressed at the timing of the mark length data TL2.

In this case, the rest detection signal RD and the note length−several multiple LEQ−
The AND circuit A11 which takes the AND condition with
When the counted value of the counter 151 matches the mark length data TL2 latched in the latch circuit 10 in the comparison between In addition to the circuit OR3,
Generates the address clock signal ACK and advances the address counter by one step.

Also, AND circuits A5, A7, A10 . The output of A11 is ORed by OR circuit OR9, and OR circuit OR4 (
1) to the tempo control circuit 16 as a key-on timing signal KOT.

In the above description, the relationship between the first sound and the second sound has been explained, but the same control is performed for the third sound, fourth sound, etc.

When the automatic performance ends, the end data (all bits “1” for both pitch data TL and note length data TL2) is transferred from data memory 3.
When read, this data is detected by the end detection circuit 55 of the start/stop control circuit 5. The detection output of this end detection circuit 55 is applied to the set terminal S of the flip-flop 51 via the OR circuit OR1, and is also applied to the reset terminal R of the flip 70 knob 54 via the OR circuit OR2, setting the flip 70 knob 51. 54
Reset. As a result, the data memory 3 becomes inoperable, the address counter 4 is reset, and the play signal becomes "0".

The above operation will be explained as follows with reference to the timing chart shown in FIG. In this case, Figure 3 (
When automatic performance is executed following the score shown in a), the second note is pressed too early, and the fourth note (the rest is also 1).
(counted as a note) indicates a case where the key press timing is delayed, and the fifth note indicates a case where the key press timing coincides.

First, when the start set switch 52 of the start/stop control circuit 5 is turned on, a start set signal SS is generated as shown in FIG. 3(b). As a result, an address clock signal ACK (FIG. 3(f)) is generated, the address counter 4 advances by one step, and data DI regarding the first tone (FIG. 3(Q)) is read out from the data memory 3. This data D1 is latched by the latch circuit 6, and based on the pitch data TL1 of the latched data, the next key to be pressed on the upper keyboard 94 of the melody sound forming section 9 is displayed by a display lamp. FIG. 3(j) shows data regarding this display.

Next, when the key displayed by the display lamp on the upper keyboard 94 (the key specified by the pitch data TL1 of the data D1) is pressed, the pressed key - number of times KEQ (Figure 3 (C)
) is generated, which causes the play signal PL (Fig. 3(d)
> rises, and at the same time, address clock signal ACK is generated. Then, the code length data T L 2 of the data D1 is latched in the latch circuit 10 by the address clock signal ACK (FIG. 3(k)).The address counter 4 is advanced by one step by the address clock signal ACK, and the data memory 3 is Data D2 is read out from the data memory 3. When the data D2 is read out from the data memory 3, the latched content of the latch circuit 6 changes to data D2, and the display lamp on the upper keyboard 94 of the melody sound forming section 9 shows the data D2. This is the key specified by pitch data TL1.

In this state, if you press the key displayed by the display lamp on the upper keyboard 94 earlier than the note length specified by the note length data TL2 of the data D1, the pressed key - several times KEQ will occur at this press timing. Rapid forward stop control circuit 15
The count value of the counter 151 (FIG. 2) is the latch circuit 10.
Since the code length data T and L2 of the data D1 latched in the data D1 are not reached, the AND circuit condition of the AND circuit A5 (FIG. 2) of the fast-forward stop control circuit 15 is satisfied, and the flip-flop 1
55 is set, and a fast forward signal FF is generated (Fig. 3 (
h)). As a result, the AND circuit A4 (FIG. 1) becomes operational, and the counter 151 is rapidly counted up by the 0-count pulse φ.
8 is established, and the code length minus several times the code LEQ is generated. When the code length minus the number multiple LEQ occurs, the AND condition of the AND circuit A6 (FIG. 3) is satisfied and the address clock signal ACK is generated. By this address clock signal ACK, the latch circuit 10
The content of is rewritten into the note length data TL2 of the data D2 latched in the latch circuit 6, and the data memory 3
Data D3 is read from. Also to the AND circuit 6
The 7 lip-flop 155 is reset by the output of
The fast forward signal FF stops. That is, when the key press timing is earlier than the timing specified by the note length data memory, the tempo pulse TP is switched to the high speed pulse φ, and the automatic performance is rapidly advanced to match the progress of the automatic performance with the key press timing.

By reading data D3 from data memory 3, the latched contents of latch circuit 6 change from data D2 to D3. By the way, since the data D3 is data indicating a rest, it is detected by the rest detection circuit 8, and the rest detection circuit 8 outputs a rest detection signal RD as shown in FIG. 3(e). As a result, the counter 1 of the fast forward stop circuit 15
At the timing when the contents of 51 reach the mark length data TL2 of the data D2 latched in the latch circuit 10, the AND condition of the AND circuit A11 is satisfied and the address clock signal ACK is generated.

When address clock signal ACK occurs, latch circuit 1
The content of 0 is the data D3 latched in the latch circuit 6.
The data read out from the data memory 3 changes from data D3 to D4. The contents of the latch circuit 6 are then rewritten to the data D4, and on the upper keyboard 94 of the melody sound forming section 9, the key specified by the pitch data TLI of the data D4 is displayed by a display lamp.

Here, if the key press timing is later than the timing specified by the note length data of data D, the key press minus the number K
Comparison circuit 15 of fast forward stop control circuit 5 before EQ occurs
Since A=B holds true at 2, the AND condition for 8 is satisfied for the AND circuit at this timing, and the flip-flop 156
is set, and a stop signal ST (FIG. 3(i)) is generated. When the stop signal ST is generated, the automatic performance is stopped as described above. In this state, when the key press-several number KEQ occurs, the AND condition of the AND circuit A7 of the fast-forward stop control circuit 5 is satisfied, and the address clock signal AC'K is generated. Then, the mark length data TL1 of the data D4 latched in the latch circuit 6 is transferred to the latch circuit (5) by ○K to this address clock signal, and the address counter 4 is transferred to the latch circuit (5).
The step is advanced and the data D5 is read out from the data memory 3. Also, the output of the AND circuit A7 resets the 7-lip 70 knob 157 of the fast-forward stop circuit 5, and the stop signal ST becomes 0. This cancels the automatic performance stop. That is, if the key press timing is later than the timing specified by the note length data T' L 2, the automatic performance is stopped until a key is pressed, and the progress of the automatic performance is made to match the key press timing.

By reading the data D5 from the data memory 3, the latch data of the latch circuit 6 is rewritten to this data D5, and the melody tone forming section 9's -keyboard 941':'Oi 1 data D5') pitch data TLI'': The key designated by '1 is displayed by the indicator lamp.Then, the key indicated by this indicator lamp is the key specified by latch circuit 1.
When pressed at a timing specified by the code length data of data D4 latched to 0, the AND condition of AND circuit AIO of fast-forward stop control circuit 15 is satisfied, and address clock signal AKC is generated. That is, when the key press timing matches the timing specified by the note length data TL2, the fast forward stop circuit 5 does not apply any control to the progress of the automatic performance.

Next, the tempo control circuit 16 will be explained.

The tempo control circuit 16 controls the tempo pulse TP in accordance with the key depression tempo. That is, when the key press tempo TP becomes faster, the cycle of the tempo pulse TP is shortened accordingly, and when the key press tempo TP becomes slower, the cycle of the key press tempo TP is lengthened accordingly. This control is performed using note length data TL2 of each note latched in the latch circuit 10.
This is performed in accordance with the key-on timing signal KOT output from the OR circuit OR4.

FIG. 4 shows a detailed configuration example of the tempo control circuit 16. When a start set signal SS is generated from the start/stop control circuit 5 (FIG. 1) and then a play signal PL is generated, the initial tempo oscillator 160 is first activated. The set initial tempo pulse is output. An initial tempo pulse of a preset frequency output from the initial tempo oscillator 160 is applied to six inputs of the selector 161. Further, the start set signal SS output from the start set circuit 5 is applied to the reset terminal latch of the flip 70 knob 162,
Flip-flop 162 is reset. The output of the flip-flop 162 is inverted by the inverter IN6, and the AND circuit A12 is activated by the play signal PL.
The signal is applied to the eight select terminal SA of the selector 161 via. Therefore, the selector 161 selects the play signal PL.
When becomes "1", the initial tempo pulse output from the initial tempo oscillator 160 is selected and output.

The initial tempo pulse is used in the initial state until it becomes possible to form a tempo pulse based on the key pressed tempo (in this case, until the fourth note is pressed), and when a predetermined condition is met, the tempo pulse changes to the key pressed tempo. Based on following tempo oscillator 1
63.

Note length data TL2 regarding the first note latched by the latch circuit 10 by the address clock signal ACK output from the OR circuit 0R3 (FIG. 1) based on the press of the first note.
is applied to variable frequency divider circuit 164. Variable frequency divider circuit 16
4 is a clock pulse φ corresponding to this mark length data TL2.
, and outputs a pulse signal having a period corresponding to the code length data TL2, that is, a pulse signal having a high frequency when the code length data TL2 is small, and a pulse signal having a low frequency when the code length data TL2 is large. The output pulses of this variable frequency divider circuit 164 are counted by a counter 165. The reason why the variable frequency divider circuit 164 forms a pulse signal with a period corresponding to the note length data TL2 as described above is to make the count value of the counter 165 that counts this pulse signal a value that does not depend on the note length data. It is. That is, the counter 165 sends the key-on timing signal KOT to its reset terminal r as a delay flip 70 tube DF.
A signal delayed in step 4 is added, and its count value is reset every time the key-on timing signal KOT occurs, but at the time of reset, the count value of the counter 165 has a constant key press tempo. If the value is constant regardless of the note length, then the value is constant regardless of the note length.

The value corresponding to the key depression tempo counted by the counter 165 is sequentially transferred to the latch circuits L1, L2, and L3 by the key-on timing signal KOT.

In addition, the key-on timing signal KOT is the AND circuit A13.
is applied to the clock terminal GK of the counter 166 through the counter 166, and is sequentially counted. This counter 166 is composed of a 3-bit shift register and outputs a carry signal when the count value reaches 4. Further, this carry signal is sent to the AND circuit A via the delay flip-flop DF5 and the inverter IN7.
13, and added to the subsequent AND circuit A13,
The subsequent operation of AND circuit A13 is prohibited.

The operations of the latch circuits Ll, L2, L3 and the counter 166 will be explained below according to the timing chart shown in FIG.

In the case shown in Fig. 3, the key-on timing signal KOT is
As shown in the figure ()), it is generated in synchronization with the key press timing. However, it should be noted that although the key is not pressed for a rest, the key-on timing signal KOT is generated at the start timing of the rest. That is, rests are evaluated in the same way as keys to be pressed, and a KOT based on the key-on timing is generated. First, while the note length data TL2 regarding the first note is latched in the latch circuit 10, the counter 165 counts pulse signals having a period corresponding to the note length data TL2. Then, this count value C1 is transferred to the latch circuit L1 by the key-on timing signal KOT regarding the second tone (FIG. 3(I)). Similarly, counter 16
5 is the note length data TL regarding the second note in the latch circuit 10.
Count pulse signals with a period corresponding to 2. This count value C2 is the key-on timing signal K for the third tone.
The content C1 of the latch circuit 1 is transferred to the latch circuit L2 by the OT, and the content C1 of the latch circuit 1 is similarly transferred to the latch circuit L2 (FIG. 3(n)). Similarly to Lx, when the key-on timing signal KOT related to the 4th note occurs at Shun, the latch circuit L
1 becomes the count value C1 (FIG. 3(o)), the content of the latch circuit L2 becomes the count value C2, and the content of the latch circuit L3 becomes the count value C3.

Further, the count value of the counter 166 is counted up in response to the key-on timing signal KOT, and when the count value reaches 4, the count is stopped.

The outputs of the latch circuits L1, L2, and L3, in which the values related to the key press tempo are latched as described above, are sent to the averaging circuit 167.
The average is taken at , and added to the latch circuit L4. Further, the output of the averaging circuit 167 is a double circuit 168a and a 1/2 circuit 1.
68bT' are respectively doubled and halved and the comparison circuit 1
69 B and C inputs. Comparison circuit 16
9 has the output of the counter 165 added to the six inputs,
When the value applied to these six inputs is between the value applied to the eight human forces and the value applied to the C input, a signal "1" is output. This signal II I T+ is applied to the AND circuit A14. The AND circuit A14 has other inputs including the output of the counter 166 and the key-on timing signal KOT.
has been added. Therefore, the AND circuit A14 determines that the count value of the counter 165 is between the double value and the 172 times value of the output of the averaging circuit 167, and that the count value of the counter 165
On condition that the count value of has reached 4, the AND condition is satisfied at the timing when the key-on timing signal KOT is added, and the signal P1''' is output.The output of this AND circuit A14 is the strobe terminal set of the latch circuit L4. and the set terminal S of the 7-lip flop 162. That is, the latch circuit L4 indicates that 1) the latch circuits L1, L2, and L3 are filled with data;

2) The count value of the counter 165 does not deviate significantly from the output value of the averaging circuit 166.

Under the condition, the output of the averaging circuit 167 is latched at the timing of the key-on timing signal KOT. Latch circuit L4
The value latched in is applied to the follow-up tempo oscillator 163. The follow-up tempo oscillator 163 is composed of a variable frequency dividing circuit, and generates a clock pulse φ according to the output of the latch circuit L4.
By dividing the frequency of the tempo, a follow-up tempo pulse that changes in accordance with the key depression tempo is generated. This follow-up tempo pulse is applied to the B input of selector 161.

Further, by applying the output of the AND circuit A14 to the set terminal S, the flip-flop 70 knob 162 is set, and the output Q of this flip-flop 162 is applied to the B of the selector 161.
It is applied to the input select terminal SB. Thereby, the selector 161 selects the follow-up tempo pulse to be added to the B input and outputs it as the subsequent tempo pulse TP.

The reason why the latch circuit L4 is designed not to latch the output of the averaging circuit 167 when the count value of the counter 165 deviates greatly from the output value of the averaging circuit 166 is because the tempo deviation of only one note is large. This is to prevent the frequency of the tempo pulse from changing even if it occurs.

FIG. 5 shows an example of the configuration of the tempo control circuit 16. In the configuration example shown in Figure 4, the evaluation was the same for any key press timing regardless of the note length, but in this configuration example, the degree of influence on the follow-up tempo pulse is changed depending on the note length. I try to let them do it. In other words, when evaluating the key tempo by converting it into a value that does not depend on note length, if short note lengths and long note lengths are treated the same, the effect on the tracking tempo pulse will be greater for shorter note lengths. Therefore, the structure is such that long note lengths have less influence on the follow-up tempo pulse than short note lengths. In the explanation of FIG. 5, parts that perform the same functions as the circuit shown in FIG. 4 are given the same reference numerals to simplify the explanation.

In this configuration example as well, the selector 161 first selects the initial tempo oscillator 1 that is applied to the six inputs until a predetermined condition is satisfied.
60 output is selected and output. That is, when each bit output of each stage of the shift register 24, which will be described later, is added, the output of the OR circuit 0R10, which takes the OR condition of the outputs of the NOR circuits NRI to NRn, is II 1 u. If there is a stage in which all bits of the parallel output are 1'', this signal is applied to the 6-input select terminal SA of the selector 161,
The selector 161 selects the initial tempo pulse output from the initial tempo oscillator 160 and outputs it.

On the other hand, the note length data TL2 latched by the latch circuit 10
is added to the variable frequency divider circuit 164, and the variable frequency divider circuit 16
4, a pulse signal having a period corresponding to the code length data TL2 is generated. This pulse signal is counted by a counter 165 that is reset every time the key-on timing signal KOT is counted, and the latch circuit 2
It is latched to 5. The value latched in this latch circuit 25 is added to the shift register 24.

The shift register 24 is composed of n stages and m bits, and takes in the values latched by the latch circuit 25 in the number of stages corresponding to the code length.

The shift register 24 has a clock pulse φ applied to its shift terminal via an AND circuit A15 which is enabled to operate according to the output of the flip-flop 26 set by the key-on timing signal KOT and the play signal PL. When the 7-lip flop 26 is set, the values latched in the latch circuit 25 are sequentially taken in. Further, the note length data TL2 latched in the latch circuit 1° is latched in the latch circuit 27 by the key-on timing signal KOT.
The counter 28 to which the key-on timing signal KOT is applied to the reset terminal R starts counting clock pulses φ in synchronization with the key-on timing signal KOT, and the output of the latch circuit 27 and the output of the counter 28 are compared in a comparison circuit 29. .

When the count value of the counter 28 reaches the note length data TL2 latched by the latch circuit 27 and a matching output is generated from the comparison circuit 29, this -spread output is applied to the reset terminal R of the flip-flop 26, and the flip-flop 26 Reset. As a result, the AND circuit A15 becomes inactive and the shift operation of the shift register 24 is stopped. That is, the number of stages to which the data latched in the latch circuit 25 is shifted in the shift register 24 for one key-on timing signal KOT increases as the note length data TL2 is large, and decreases as the note length data TL2 is small.
The number corresponds to L2. For example, if the note length data TL2 corresponds to a quarter note, and the shift register 24 takes in data for 2 stages, then if the note length data TL2 corresponds to a stupid note, then the data for 2 stages is taken into the shift register 24. Data is captured. The contents of each stage of this shift register 24 are stored in the averaging circuit 167.
An average value is taken at , and added to the follow-up tempo oscillator 163.

Assuming that each stage of the shift register 24 is filled with data, when the data related to the first note reaches the final stage of the shift register 24, the output of the OR circuit 0RIO becomes "OTT", and the output of the OR circuit 1o is sent to the selector 161 via the inverter N8. As a result, the selector selects a follow-up tempo pulse based on the pressed key tempo output from the follow-up tempo oscillator 163, and outputs this pulse from now on.

FIG. 6 shows a further example of the configuration of the tempo control circuit 16, in which the tempo pulse is corrected based on the deviation between the note length data TL2 and the note length formed by the tempo pulse. There is. In this configuration example, the tempo pulses are generated by a voltage controlled oscillator (VCO) 30. ■C030 is equipped with terminal A for manual tempo setting and terminal 8 for correction, and terminal A for manual tempo setting.
An initial tempo is set by a manual tempo setter (variable resistor) 31. The tempo pulse output from vC030 is applied to the clock input of canter 32. The counter 32 has a key-on timing signal KOT applied to its reset terminal R, is reset every time the key-on timing signal KOP is received, and counts tempo pulses TP. The tempo pulse TP count value of this counter 32 corresponds to the note length formed by the tempo pulse TP. The count value of counter 32 is added to the input of subtracter 33B.

The subtracter 33 has six inputs to which the note length data TL2 latched in the latch circuit 10 is added, and subtracts the C1 value of the counter 32 from this note length data TL2. This subtraction value IA-Bl and a signal indicating its code length are applied to the latch circuit 34.

Further, the subtracted value IA-81 output from the subtracter 33 is added to the allowable value detection circuit 35. The allowable value detection circuit 35 compares the preset allowable value and the subtracted value +A-B+, and if the subtracted value is within the allowable value range, outputs a signal "1" to the AND circuit A.
Add to 16.

The AND circuit A16 has the key-on timing signal KOT added to its other input, and outputs the signal "1'' in synchronization with the key-on timing signal KOT on the condition that the subtracted value in the subtracter 33 is within the allowable range. This signal is applied to the strobe terminal S of the latch circuit 34.

That is, the latch circuit 34 outputs the key-on timing signal KO on the condition that the output of the subtracter 33 is within the allowable range.
The output of the subtracter 33 is latched at timing T.

The reason why the tolerance value detection circuit is provided here is to prevent the tempo pulse from following large changes in the key depression tempo. The output of the latch circuit 34 is converted into an analog signal by a digital-to-analog converter 36 and applied to a correction terminal B of the VCO 30.

Although the latch circuit has one stage in the configuration example shown in FIG. 6, it may have multiple stages as in the configuration example shown in FIG. 4, and an averaging circuit for taking the average value may be provided.

FIG. 7 shows another embodiment of the invention. In this implementation sequence, when the key press timing is later than the note length data, or when they match, the operation is the same as the example shown in Figure 1, but when it is early, the reason for automatic performance is determined by the rhythm counter. Preset directly to 4): configured to. In the description of FIG. 7, the same parts as in FIG.

When a start set switch (not shown) is pressed in the start/stop control circuit 5, the data memory 3 becomes operational and the reset of the address counter 4 is released. Further, a start set signal SS is generated from the start/stop control circuit 5, and this signal SS is supplied to the OR circuit 0.
It is applied to the clock terminal CK of the address counter 4 as an address clock signal ACK via R11, and advances the address counter 4 by one step. As a result, data D1 regarding the first sound is read out from the data memory 3,
A signal obtained by delaying the address clock signal ACK by the delay circuit 7 is latched by the latch circuit 6. The signal latched by the latch circuit 6 is applied to a rest detection circuit 8 to detect a rest, and is also applied to a melody sound generation section 9 to display the key of the first note.

When the key of the first note is pressed in this state, a matching output is generated from the comparator circuit 12, and the AND circuit A1 becomes operable.
A key press-number multiple number KEQ is outputted via the select switch 14. This pressed key - number multiple number KEQ is first applied to the start/stop control circuit 5 to output a signal indicating the pressing of the first tone key, and this signal is sent to the address counter 4 as an address clock signal ACK via OR circuits 0R12 and 0R11. clock input. Also, OR circuit 0R1
The output of 1 is applied to the strobe terminal S of the latch circuit 10, and the note length data TL2 of the data related to the first note latched in the latch circuit 6 is latched. Also, the output of the OR circuit 0R11 is the reset terminal R1 of the counter 151.
It is applied to the preset terminal PE of the down counter 37 and the preset terminal PE of the rhythm counter 38. As a result, the counter 151 is reset, and the down counter 37
The note length data TL2 latched in the latch circuit 10 is preset. Note that at this time, the rhythm counter 38 is preset to an initial value.

In this state, if the next key press timing is earlier than the note length data TL2 latched in the latch circuit 10, the counter 151 which forms the tempo pulse TP output from the tempo control circuit 16 via the AND circuit A17. In the comparison circuit 152 that compares the count value and the output of the latch circuit 10, A>8 holds true, and the AND condition of the AND circuit A18 holds true. The output of this AND circuit A18 is sent as an address clock signal ACK via OR circuits 0R13, 0R12, 0R11.By the way, the down counter 37 and rhythm counter 38 are added with the tempo pulse TP output from the AND circuit A17. , counts down and counts up in response to this tempo pulse TP. Therefore, in this case, the count value n of the down counter at the time when the output is generated from the OR circuit 0R11
is n>o. The count value n of this down counter 37 is 1 mN of the count value of the rhythm counter 3B in the adding device 39.
The added value N+n is preset in the rhythm counter 38 at the output timing of the OR circuit 0R11. That is, by presetting the addition value N++1 in the rhythm counter 38, the delay value n of the rhythm counter 38 with respect to the key press timing is eliminated. Also, OR circuit 11
The counter 151 is reset by the output, the note length data TL2 regarding the next note is latched in the latch circuit 10, and the note length data TL2 latched in the latch circuit 10 is preset in the down counter 37.

Next, if the key press timing is late with respect to the note length data TL2 latched in the latch circuit 10, the key press-several code KE
Before Q is generated, A=B is established in the comparator circuit 152, and the code length-number multiple LEQ is generated from the differentiator circuit 156. As a result, the AND condition of the AND circuit A19 is satisfied, and the flip-flop 157 is set. this flip 70
Output Q of knob 157 is applied to AND circuit A17 via inverter IN3, rendering AND circuit A17 inoperative. That is, the tempo pulse TP is stopped, and the progress of the automatic performance is stopped. Further, the output Q of the flip-flop 157 is applied to the AND circuit A20 via the delay flip-flop DF3. This AND circuit A20 is a key pressed -
Signal II I IT at the timing when several multiples KEQ occurs
is output, and the address clock signal ACK is generated from the OR circuit 0R11. At this time, the count value n of the down counter 37 is n=o. Therefore, the outputs of the three adders remain the count value N of the rhythm counter 38, and this value N is preset in the rhythm counter 38 by the output of the OR circuit 0R11. Further, the output of the AND circuit Δ20 presets the flip 70 knob 157. As a result, the AND circuit A17 becomes operable and the stoppage of automatic performance is canceled.

When the key press timing matches the note length data TL2 latched in the latch circuit 10, the AND condition of the AND circuit A21 is satisfied and the address clock signal ACK is generated from the OR circuit 0R11. J, the count value n of the down counter 39 is no, and the value preset in the rhythm counter 38 by the output of the OR circuit 0R11 remains the count value N of the rhythm counter 38. In other words, no control can be applied to the progress of automatic performance.

Further, when a rest is detected by the rest detection circuit 8, the comparison circuit 1
52, A=8 is established, and the AND condition of the AND circuit A22 is established at the timing when the sign length-number multiple LEQ occurs, causing the OR circuit 0R11 to generate 0K in the address clock signal.

Further, in this embodiment, the key-on timing signal KOT used in the tempo control circuit 16 is obtained from the output of the OR circuit 0R12.

As explained above, according to the present invention, when the key pressed on the keyboard deviates from the normal performance, the progress of the automatic performance is stopped in response to the timing of this key depression, and this stop is changed to the normal performance. Since the process continues until a matching genuine key is pressed, it is possible to match the progress of the automatic performance with the genuine key pressing timing, which is particularly useful for practicing performance. If the notes are continuous, note length data and pitch data may be formed by treating these notes as one note. With this configuration,
Tempo stability can be achieved when there are consecutive notes with extremely short note lengths.

Alternatively, data may be created by extracting only important notes from the melody sounds. In this case, data can be simplified.

Further, the fast-forward clock generated when the key press timing is early may be made to follow the tempo, be made to speed up exponentially when the note lengths match, or be made to slow down exponentially for a restart. This makes it easier to follow the performance.

Furthermore, when controlling the frequency of the tempo pulse using n pieces of past tempo data, each of the n pieces of data may be weighted. For example, natural tempo control can be achieved by giving greater weight to similar data.

Furthermore, it goes without saying that the musical score data that forms the basis of automatic performance can be implemented in the same way with data related to the beta keyboard or the lower keyboard.

In addition, in this embodiment, the automatic performance melody sound forming circuit always monitors and sounds the melody sound to be played one note earlier, making it easier for the performer to play the melody, but the obbligato data is not stored. An obbligato generation circuit may be provided to automatically play the obbligato to assist the performer's performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is a circuit diagram showing a detailed configuration example of the fast forward stop control circuit shown in Fig. 1, Fig. 3 is a timing chart explaining the operation of the device shown in Fig. 1, and Figs. 7 is a block diagram showing a detailed configuration example of the tempo control circuit shown in FIG.
The figure is a block diagram showing another embodiment of the invention. 1... Musical score, 2... Musical score data reading device, 3...
Data memory, 4...Address counter, 5...Start/stop control circuit, 6.10...Latch circuit,
7... Delay circuit, 8... Body step detection circuit, 9... Melody sound forming section, 11... Sound system, 12.
... Comparison circuit, 13 ... Differentiation circuit, 14 ... Select switch, 15 ... Fast forward stop control, 16 ... Tempo control circuit, 17.38 ... Rhythm counter, 21
... Accompaniment sound forming section, 37 ... Down counter, 39
...adder.

Claims (1)

[Scope of Claims] <1) A storage means and a keyboard for storing pitch information and note length information corresponding to notes to be played; and a keyboard for sequentially reading out the note length information from the storage means in the order of performance, and reading means for reading out information prior to performance; automatic performance means for performing a predetermined automatic performance; and a next operation designated by the pitch information even when the designated timing designated by the note length information has come. an electronic musical instrument comprising automatic performance stopping means that stops the automatic performance in synchronization with the instruction timing when the desired key is not operated and maintains this stopped state until the key is operated next time. (2) The automatic performance stopping means includes a counter that counts predetermined clock pulses starting from the time when the note length information is read by the readout means, and the count value of the counter and the note length information match, and and a storage device that is set to one state when a key indicated by the pitch information has not yet been operated, and is set to the other state when the key is operated, and the automatic performance is based on the output of the storage device. Claim 1 (1) in which the progress of the automatic performance of the device is controlled to stop.
Electronic musical instruments listed in ). (3) The electronic musical instrument according to claim (1), wherein each of the tones to be played is a melody tone. (4) The automatic performance means controls the progress of automatic performance in accordance with the count value of a tempo counter that counts tempo pulses, and the automatic performance stop means controls the supply of tempo pulses to the tempo counter. The electronic musical instrument according to claim (1), which prohibits the above. (5) The electronic device according to claim 1, wherein the automatic performance means is characterized by at least one automatic performance sound selected from automatic rhythm sounds, automatic bass sounds, automatic chord sounds, and automatic albejo sounds. musical instrument. (6) The electronic musical instrument according to claim (1), wherein the automatic performance means produces musical tones corresponding to pitch information and note length information read by the reading means. (7) a storage means for storing pitch information and note length information corresponding to notes to be played; a keyboard; and a keyboard, for sequentially reading out the note length information from the storage means in the order of performance and for pre-playing the pitch information. a reading means for reading the pitch information, a display means for displaying a key to be operated in accordance with the pitch information read from the successive reading means, and an automatic performance means for performing a predetermined automatic performance;
If the key to be operated next as indicated by the pitch information is not operated even at the instruction timing indicated by the note length information, the automatic performance is stopped in synchronization with the instruction timing and the key is An electronic musical instrument comprising automatic performance stop means that maintains this stopped state until the next operation. (8) The electronic musical instrument according to claim (7), wherein the display means includes light emitting means corresponding to the duplicate keys, and one is provided at a predetermined position of the duplicate keys. (9) The electronic musical instrument according to claim 1, wherein the display means includes light emitting means corresponding to each key, and is arranged near the duplicate keys.