JPS5829220A - Analog voltage output device - Google Patents

Abstract

PURPOSE:To obtain plural voltage outputs through a simple circuit by connecting voltage follower circuits to respective outputs of an analog multiplexer, and converting digital signals which correspond to the respective outputs through one digital-to-analog converter. CONSTITUTION:A microcomputer 4 selects one of switches SW0-SW7 of an analog multiplexer 7 and also applies a digital signal which corresponds to the selected switch to a digital-to-analog converter 1. The output of the converter 1 is converted by a converter 2 into a voltage, which is applied to the multiplexer 7 and then outputted to one of voltage follower circuits 8-15 through the selected switch. A digital signal is applied cyclically to the converter 1, so output voltages (a)-(h) have less errors.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a 7-order voltage output device, and more particularly to an analog voltage output device that converts a plurality of digital signals into a plurality of corresponding 7-segment voltages and outputs the converted signals.

Conventionally, when outputting a digitally processed signal to the outside as a 7p dummy positive value, a digital-to-anap converter is used to convert the digital signal to a 7p dummy voltage.
A device was installed that outputs to the outside using a Bolden-Four circuit or an impedance converter.゛An example of such a conventional 7 Nag voltage output device is shown in the tl.
! Mizuko on l11. In the figure, 1 is a digital 7spG converter (hereinafter referred to as DA converter), and 2 is a current/voltage converter that receives the analog output current of DA converter 1 and converts it into voltage. 3 is an operational amplifier as a voltage 7 lower circuit or an impedance converter.

As is clear from the figure, the digital signal input to the D-A converter lk is converted into an analog current there,
Further, it is converted into an analog voltage in a current/voltage converter 2.

Impedance conversion works well to output an output voltage equal to the input voltage. In this case, the output impedance of impedance conversion@3 is sufficiently low, so by choosing the value of its input resistor 8 sufficiently large, the output voltage can be kept constant k (i.e., its input voltage ) can be maintained.

When a 7-order voltage output device using such a conventional DA converter is used, a stable analog voltage can be obtained as an output. However, in this device, there is a one-to-one correspondence between input and output, so when there are multiple outputs, the same number of D-A converters as the number of outputs, the current
Requires a set of voltage converters and impedance converters.

Therefore, the circuit becomes complicated, which not only increases cost but also reduces reliability.

An object of the present invention is to improve the above-mentioned drawbacks of the conventional device, to reduce the complexity of circuit configuration and high cost as much as possible, to convert a plurality of digital signals into a plurality of corresponding analog signals, and to convert each digital signal into a plurality of corresponding analog signals. There are some devices that provide analog voltage output devices that can output voltages.

In order to achieve the above object, in the present invention, one terminal of each of a plurality of commonly connected analog switches,
An analog voltage obtained by DA conversion is applied, this analog voltage is held for a predetermined time, and the plurality of analog switches are periodically and cyclically activated.

Furthermore, in the present invention, a third hold circuit is connected to each hold circuit via a rattan 2-piece wire so as to suppress fluctuations in the output voltage as much as possible.

The present invention will be described in detail below with reference to the drawings. Second
The figure is a boot diagram showing an embodiment of the present invention. In this figure, the same reference numerals as in FIG. 1 represent the same or equivalent parts.

In the figure, numeral 4 is a microphone ρ/p/-ta, 7 is an anag multiplexer including a 7 pg switch 5WoNSW, and 8 to 15 are operational amplifiers as voltage follower circuits or impedance converters. Each voltage follower circuit has its own hold capacitor Co/
-C, constitutes a voltage hold circuit.

The circuit elements that the inventor experimentally included in the circuit configuration shown in FIG. 752 are as usual.

D-mu converter...NEC μPD624
D Mike Combi - Evening 4 - NEC It JPDI
511 Anada multiplexer 7...Toshiba C40
51BP Next, the circuit operation of the embodiment shown in FIG. 2 will be explained with reference to the 311th timing chart.

For the microphone combination and evening, as shown in the timing chart shown in *smwc, the signal for analog switch specification, B.
, outputs C.

Here, the signals M, B, and C can be considered as binary numbers,
When all of the signals M, B, and C are 101, the 28th
The analog switch SW· is designated and closed, and the other analog switches SW1 to SW8W are held in the open state i1. When signal M, B, and C are all 111, 8
The 7-channel switch 8W shown in FIG. 11 is designated and closed, and the remaining 7-spring switches SW0 to 8W6 are opened.

At time T, the microcomputer 4 outputs a signal M=
O, B=O, C=0 are outputted and supplied to the C7spg multiplexer 7. This allows the 7 nag multiplexer γ
Analog switch SW inside.

is specified.

Also, at the same time, the microphone combination 4 is connected to the output terminal aW.
The 8-bit data signal that corresponds to the voltage to be output from C is
Send from mukon meter 1#c. The D-mucon converter l converts this signal into an anagummy source signal. The Analog source signal is subjected to seven-digit voltage compensation Yak conversion by an amplifier 92, and is supplied to the common connection terminal of the Analog multiplexer 7 via a resistor R1.

At time T, JIC, the microcomputer 4 sets the inhibit terminal IN)I of the ANADA multiplexer 7 to L (low) level. Then, the analog switch 8W6 in the analog multiplexer 7 specified earlier
is closed, and the analog voltage Va is supplied to the input terminal of the voltage follower 1 circuit 8.

At time ↑, the I/HIBIT terminal INH of the ANAG multiplexer 7 is set to H (high) level, and the NARG switch 7 and 8W are opened. Thereafter, the analog output voltage Va is held by the hold IgI circuit consisting of the capacitor C and the voltage follower circuit 8 until the analog switch 8W is closed again.

At time i4, my tar combination is 4:1. B
:O, C:O is output, and the 7-seg switch SW in the analogue pg multiplexer 7 is specified.

At the same time, the anagummy pressure vb that should be output from the 1st output terminal bk
#IC#l digital signal to D-M converter I
K supply. The digital signal is converted into an analog voltage VbK and then supplied to the common terminal of the analog multiplier 7.

At time TI, the microphone combination 4 sets the inhibit terminal INH of the 7-nag multiplexer 7 to the L level KL, and opens the analog switch SW in the 7-nag multiplexer f7 designated at this time. As a result, a seven-nag voltage vb is applied to the input terminal of the voltage follower 1 circuit 9.

At time T, the inhibit terminal INH of the analog multiplexer 7 is set to H level and the analog switch 8 is turned on.
Open W1. After that, analog switch 8 again
Until W1 is closed, analog output voltage vb is held by a hold circuit consisting of capacitor C8# and voltage follower 1 circuit 9.

Thereafter, in the same manner, the output terminal c P-h IIc l@the analog voltage V e -V h to be supplied next is outputted.

- Once the output has been completed, voltage supply is started again in order from the output terminal α.

Generally, when a circuit like the one-circuit-two diagram is used, if the capacitance of a certain capacitor c0 to C1 used in the hold circuit is large, the voltage holding characteristics will be poor.

However, on the other hand, if the capacitance of the capacitor is increased (then
These capacitors C, -, -C and current limiting resistor R,
It is formed by Since the time constant of the integral (b) path becomes large, the response time becomes long. In other words, each co/den?
It takes kIk time for the terminal voltages of C. to C7 to reach a predetermined value and stabilize (hold).

5. Under conditions where the response time of each hold circuit is critical, if the hold voltages of all hold circuits are updated cyclically and periodically as described above, the voltage update will be difficult. There is a problem that the time interval is too short and it is impossible to follow signals with a large rate of change.

As a solution to this problem, the analog switch 8 Wo' is used only when the microphone-computer 4 digital signal changes and the output needs to be changed accordingly.
It is conceivable to close this one of the = S Wy and generate an analog voltage updated as described above at the scissors output terminal.

However, in this method, the update period of the output with a small rate of change becomes long, so the fluctuation in the output voltage becomes large due to the leakage current of the hold circuit. Moreover, the fluctuation range has a drawback that it varies because the output terminal a−h<.

Furthermore, the range of variation in the output voltage not only differs depending on the data update time, but also varies from circuit to circuit, so it is difficult to calculate vMK strictly and it is not easy to compensate.

Therefore, as in the embodiment of the present invention described above, the anagummy pressure is cyclically outputted from the output terminals 1 to hK regardless of the presence or absence of a change in the output voltage. This means that it is desirable to make it smaller.

Also, when updating the output voltage cyclically like this, if the time for one switching/scanning cycle is shortened,
There is also an advantage that the value of the hold capacitors C to C can be made small, and changes in the output voltage can be transmitted quickly.

However, the time for one cycle of switching and scanning described above is D
- Muco/meter conversion time (settling time),
Response time of operational amplifiers 2.8 to 15 as current/voltage co/parter and voltage 7 lower circuits, or 7
It is clear that the response time of the switch 8W.about.SW is limited.

By the way, out of the amount of charge flowing into (or flowing out to) the capacitors C0 to C, K, the analog multiplexer 7, and the operational amplifiers 8 to 15 forming the voltage hold circuit as shown in FIG. The factor that has the highest contribution rate to the variation of vh is due to the leakage current from the analog-jigging multiplexer 7 to each capacitor C0 to C1, or the leakage current from each capacitor C0 to C7 to the analog-jigging multiplexer 7. It has been known.

The leakage current is said to be proportional to the square of the potential difference between the voltage at the common input terminal of the analog multiplexer and the voltage at the opposite terminal of each analog switch, that is, the analog output voltage. Therefore, by connecting the voltage hold circuits in two stages, it becomes possible to suppress the variation in the analog output voltage kj# even more minutely.

Another embodiment of the present invention based on such ideas and considerations is shown in FIG. In this figure, the same reference numerals as in FIG. 2 represent the same or equivalent parts.

Comparison with Figure 2 shows that the digital signal from the microcomputer 4 is converted to an analog current by the DA converter 1, and this is converted into an analog current by the 7 nag switch 8 Wo.
= After SW Ma, #Roaring Voltage 7 respectively
Until it is transmitted to the output side of the power supply circuits s to Is, it is the same as in the 111th embodiment described above.

In addition, in the example 41mf)II, the selection and energization of each analog switch 8Wo to 8Wt is shown to be performed by the individual control output SC. However, it is true that it may be replaced by a multiplexer similar to the 21st il.

In III#c, 20-17 are resistors R1 corresponding to the outputs of the ports 4-797 S to 1s, respectively.
・~R1? A second 7nard switch is connected via the 7nard switch. These analog switches 30 to 7 are for controlling the aforementioned analog switches 8W to BW.
Combi, control output from -Y4 8C.~80. Similarly, WCB is selected and activated.

C1.~C1 are each of the second 1 p da switch 1G-
17 output terminal side Km connected hold capacitor,
30 to 37 are voltage forward circuits, and the six pairs of the hold capacitor and the voltage forward circuit constitute a first voltage hold circuit.

As mentioned above in the example 1cm1l of FIG. 1, the input ends of the analog switches 8W and -8W are commonly connected,
Seven Naag voltages Va to vh are applied periodically and cyclically.

Therefore, as is clear, each analog switch 8W,
The potential difference between the input side (common connection) terminal and the output side terminal of ~8W becomes relatively large. That is, a large amount of charge flows out from the capacitors C0 to C, K constituting the voltage hold circuit, and the fluctuation of the hold voltage becomes large.

On the other hand, in the second 7-spring switches 20 to 27, the potential difference between the input side terminal and the output side terminal is extremely small, so the power capacitors C1° to C
The inflow or outflow charge amount of tV becomes extremely small. Since the third stage, the signal hold characteristic becomes good, and it becomes possible to suppress fluctuations in the anarch output voltage at each of the output terminals 1 to hK to an extremely small level.

It is clear from the above explanation that according to Honji 1jiK,
Even if there are a plurality of anarch output signals, it is sufficient to use only one D-me converter, thereby simplifying the circuit and reducing costs.

Furthermore, since there is no need to take into account variations in the characteristics of the D-me converter, assembly and adjustment can also be simplified.

[Brief explanation of drawings]

Figure 111 is a block diagram of a conventional analog pg voltage output device.
Figure 2 is a block diagram of an embodiment of the present invention, and Figure 3! II is a tile blowfish chart to explain its operation, 4th E
is a block diagram of another embodiment of the present invention. l.-D-me converter, to.. current/voltage converter, 4.. microcomputer, 7.. 7spg multiplexer, 8-15.30-37.. voltage 7 oh circuit, 20-. 27, SW, ~SW,...
Analog switch, axh... Analog voltage output terminal. Agent: Patent attorney Michi Hiraki (1 non-person)

Claims (1)

[Claims] (l) A digital-to-anada converter that receives a digital signal and outputs an analog voltage; and a plurality of analog switches each having one terminal commonly connected to the output of the digital-to-anada converter. , a plurality of voltage hold terminals each connected to the other terminal of each of the analog switches, and means for cyclically energizing each of the analog switches. (2) a plurality of analog switches each having one terminal connected in common to the output of the digital to seven-speed pda converter; a plurality of voltage hold circuits each connected to the other terminal of the analog switch; and a plurality of JLL voltage hold circuits each connected to the output end of each of the plurality of voltage hold circuits via a iris analog switch. , and means for cyclically energizing each of the analog switches and the second analog switch.