JPS5831397A - Voice signal processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a written signal relaxation device that compresses and expands an audio signal on the time axis, and particularly to a novel circuit configuration that makes it applicable to a real-time frequency conversion device of an audio signal. It provides:

When recording and reproducing audio signals using a recording medium such as a tape recorder, it is sometimes desired to change the reproduction speed to the recording speed. In this case, the frequency structure of the reproduced audio signal naturally changes depending on the ratio (Map 1) between the reproduction speed (MAP) and the recording plowing degree (MAR).

Ie each of the signals! R wave number component! (f) is map p/'fR
-x (f), but if this degree is large, the audio signal will be very difficult to hear or become inaudible.

Therefore.

Even if the playback speed changes and the playback time becomes longer or shorter, the frequency structure of the audio signal does not change. In other words, it is necessary to control the sound so that the pitch does not change. A circuit device such as this is called a time axis compression/decompression circuit. In this case, the playback speed (MAP) and the recording speed (MAR) are specifically the running speed of the magnetic tape (unit: >/a. C) In the case of a disk record, it refers to the number of revolutions of the record (units Pi, P, II), etc.

FIG. 1 shows the principle of such a circuit arrangement.

The audio signal whose time axis has changed due to high-speed reproduction or low-speed reproduction is input to the input terminal (1) K, and is sampled at the clock frequency (fl) given from the clock generator (RI).
It is sampled by the clock and stored in the memory circuit (3), and then read out according to the clock frequency (f) from the clock generator (2), and is then read out from the output terminal (51) via IJv F (4). Output.This and the above-mentioned link a tsuku (fl) and (f meaning)
If the ratio of is made equal to the above-mentioned recording/reproduction speed ratio map p/vR, that is, f1/f2 ratio map p/YR...
...... (1), the time axis of the audio signal at the input terminal (1) is corrected, and a reproduced signal with the same frequency structure as the recording signal is obtained at the output terminal (-).The audio signal Specifically, the circuit that stores the sample values of B B D
(Baokwtmrigad@Davies) C
CD (Charg@Coupledp・Ma10・), analog memory such as capacitor memory, or RAM
There are digital memories such as It on the output side?
1t4) is necessary to remove high frequency signal components included in the sample value sequence and extract only the audio signal components. (
1) Lock shoulder comb (fl) or (
In order to create a frequency f, a moderate ratio signal must be given to the clock circuit (2) from the terminal (phrase).

On the other hand, according to the sampling theorem, the desired reproduction signal ◆ma wave frequency is constant weighted by the readout clock frequency (f) and is less than half of it, so in actual configuration, it depends on the reproduction signal band ( The conventional method is to set f to a constant value and change (fl) according to the speed ratio signal.

FIG. 2 is a specific example of a circuit in which the memory circuit of the time axis compression/expansion circuit is constructed from a RAM. The input signal of the input terminal C11+ passes through I and PF (13) on the input side, is converted into a digital code by the multi-chip converter a!I with a built-in sample and hold circuit, and is sent to the write address circuit (to) of RAMQ-.
will be stored at the address specified by . Mu D conversion 11C1
A clock circuit (eP) that generates a clock frequency (ft) of a write clock such as a timing signal (so-called convert command signal) for 1 and a write address clock (18 is a clock circuit for playback of a tape recorder, which is a recording medium in this case). Control voltage generation circuit (to) that voltage-controls the speed of the motor (in the case shown, a variable resistor (voltage-controlled oscillator whose oscillation frequency is variably controlled by the output voltage of the vp) connected to a constant-voltage power supply oltag@Co
ntroll@d0soilator (abbreviated as VCO)
is the main focus. The write address circuit (to) for the RAM (14) is composed of a counter that counts the write clock.

Next, the data stored in RAMQ- is sequentially read out from the address specified by the read address circuit (2) that counts the read clock of the clock generator (2) with a constant clock frequency (fl). According to p
- LPν on the output side
(2) and is output from the output terminal (2). Gang, RAM
(The control of the write read operation for 1- (so-called R/W control) is carried out by the R/W switching circuit which receives the write and output clocks as input, and each address switching is performed by the R/W switching circuit 1). A multiplexer controlled by a circuit (
Each is carried out by a financial institution. In such a circuit configuration, the clock frequency (fl) determined by the oscillation frequency of the VCO included in the recording clock circuit is set such that the reproduction mode of the reproduction peak (2) is equal to the recording speed. For the output type WE of the control voltage generator (2), f I
III.
), if we define each characteristic so that the change in is always the same, we get (
Equation (1) is satisfied for fl) and (f, and the desired time axis compression/expansion processing without changing the audio signal frequency can be achieved.In this case, in the high-speed playback special number ζ, f 1
) f 2, and therefore, if the number of data (number of samples) of fAMg4 is y, then 2 M(1--) 1 samples are not successively extracted every cycle for the violet samples stored in this. It can be seen that the frequency of the data that remains after being discarded is multiplied by (f2/?+).

In addition, in the case of low-speed playback, since tl<t, 1 M(1--') fl samples are repeatedly read out on average, and these frequencies are multiplied by (f*/f1). .

Now, as shown in Figure 3, the spectral structure of the sample value time series sampled according to the clock of frequency (fl) has a shape that is equal to the spectrum of the input signal on both sides of an integer multiple of the sampling frequency (fz). arise.

Therefore, if the input signal has incomplete banding, the spectrum of the sampled signal will be distorted. Once the overlap occurs due to sampling, it is impossible to separate it, and the distortion caused by this overlap is called aliasing noise. What about Figure 3?
CM (hzls+e Ce1l@oaultti
oa) shows the signal nosohectoral distribution, and also has the characteristic (In)
represents the spectral distribution of the input signal, and the horizontal axis represents the frequency (illustration).

The input filter (to) in Figure 2 must be able to avoid this aliasing noise and exhibit sufficient attenuation at the frequency (fl/2).In this case, the input signal is high speed. The signal is regenerated or regenerated at low speed, and its bandwidth changes with the reproduction speed ratio KI6 as shown in FIG. At the same time, the sampling clock frequency (fl) can also be changed. Therefore, when the spectral structure changes in this way, the best way to completely avoid folding is to make (f+) sufficiently large, or to change the bandwidth of the input filter (to) according to the playback speed ratio Cq/s>K. Figure 4 shows how the spectrum of the yCM signal changes. Figure (1) shows the spectral distribution of the I'CM signal for high-speed reproduction sound, and Figure 4 (to) shows the spectral distribution of the I'CM signal for low-speed reproduction sound. It shows the spectral distribution of the PCM signal, and the characteristic (In) shows the spectral distribution of the input signal.

In general, increasing the sampling clock (fl) increases the storage capacity (b), so it is not often used from a cost standpoint, and usually the characteristics of the input filter are often changed. The input filter (2) is a voltage-controlled variable filter whose cut-off frequency changes with the speed control voltage.

Now, the present invention makes it possible to add a function as a real-time frequency conversion device for an audio signal by changing the time axis compression/expansion processing number ζ of the audio signal and its circuit configuration. That is, this is a device that is added to a music signal reproduction device and increases or decreases the sound II (pitch) of the reproduced sound by proportionally expanding or decreasing the signal frequency in real time.

For example, it can be used as a variety of musical performance equipment.

FIG. 5 is a block diagram showing the configuration of the present invention.

In the illustrated state, each switch in the figure constitutes a time-base compression/expansion circuit for audio signals, similar to that in FIG. 2. That is, the input signal from the input terminal αD passes through the switch (2), the input filter (2), the switch (to), is sampled and compressed by the multiple converter UK, is digitally coded, and is stored in the RAM. (It is stored in 14. Also, the read data is converted into analog by the D-m converter mK, and the switch (conversion), the output filter (2), the switch (
(to), and the audio is output from the output terminal (2). The clock frequency of the clock generator (to) is controlled by the control voltage (vc) K generated by the variable resistor (to), and the clock frequency (fl) is controlled by the control voltage (vc) K generated by the variable resistor (to). - As a convert command signal for the DR converter (13) and as a count clock for the write address counter (to).

Alternatively, the R/IF switching circuit 12 can be used as an R/W switching signal.
1, respectively. The read address circuit α volume and the multiplayer vehicle quantity @ are as explained in FIG.

The control voltage (Vo) of the variable resistor (Vo) changes the cutoff frequency of the variable filter (Vo) proportionally as shown in the figure, and the control voltage is (va) and the cutoff frequency is (fa). If so, f1sgkl'-7low-++@M#...song...
−・−・−・・・(rit, wxk, -vc, -----
−−−−−−−−−−−−−−−−−−−−−−@, however, kl and ! is a constant. The control voltage is input as the speed control voltage of the regeneration motor (b) via the switch (2). That is, map p species ml, = ma0 −...axis *+1””@as@
−−＠#＠−Rumor−・−−・−(4) Now, if we configure switches (2) to (2) in this way and invert them at the same time, the circuit in Figure 5 will switch. This results in Figure 6. That is, the input signal from the input terminal I passes through the switch (2), the filter (2), the switch (to), is sampled by a clock circuit (to) with a constant clock frequency (fm), and is then uniformly converted to IB. (digitally coded at 11, R
Stored in AJl#.

The attenuation characteristic of filter (2) is R wave number (fυ勺)′T! The variable clock circuit (
This frequency (fl) is determined by the control voltage determined by the adjustment position of the variable resistor. The data read out at the clock frequency (fl) is converted into an analog signal through a PM converter, and then sent through a switch (to), a variable filter (2), and an output terminal (2) from the switch (to). Output. The same wave number conversion ratio (that is, pitch conversion ratio) in this case is the ratio (f
1/? 2) Therefore, by appropriately controlling the variable resistor 11@, the output acoustic signal and pitch can be changed arbitrarily.

The cutoff frequency (fo) of the variable filter (2) connected to this output is as shown by equations (1) and +2).
The control voltage (Ma0) changes in conjunction with the clock am number (fl), and one frequency (f1/2) shows sufficient attenuation, so the part where the clock component (fl) falls within the output signal band can be ignored. meet Write and read address circuits LHI and (to), J multiplexer for switching addresses, and R/W circuits Part 2
This is as explained in the figure.

This invention is here! ! A clock circuit with a constant frequency, a variable clock circuit and a variable filter circuit whose clock frequency and filter characteristics can be controlled in conjunction with each other from the outside, and a filter circuit whose filter characteristics are fixed can be switched by a switch circuit. Since the time axis conversion circuit and the frequency conversion circuit of a signal can be constructed using the same circuit components, it is possible to realize a versatile acoustic signal processing device.

[Brief explanation of the drawing]

Figure 1 is a block diagram for explaining the principle of time axis correction, Figure 2 is a block circuit diagram of the time axis compression/expansion circuit, and Figure 3 is a block diagram for explaining the principle of time axis correction.
Figure 4 shows the PCM in the sampling value time series.
FIG. 5 is a block circuit diagram showing the audio signal processing device of the present invention, and FIG. 6 is a block circuit diagram showing the device when the device is switched. (Lm--signal input terminal, @...variable filter, a to p converter, as-...RMM, (to) αF...address circuit. (to)...variable frequency clock generation Circuit, Q?)-・
・Motor, (to) ・- Fixed frequency clock generation circuit, (
To)...D-mu converter, (2)...L,? ,? , , (2)...Signal output terminal, (To)...R/W switching circuit, (To)...Multiplexer, (To)...Control voltage generation circuit.

Claims (1)

[Claims] (1) A storage means including an input clock terminal, an output clock terminal, and a storage circuit for sampling and storing an acoustic signal according to one external clock and clocking out according to the other external clock, and a clock frequency controlled by an external control signal. a first clock generating means that is variably controlled, a second clock generating means having a fixed clock frequency, and a variable filter means whose attenuation characteristic changes in conjunction with a change in the clock frequency of the interlock generating means; a first switch circuit means for switching the first and second clock generation means between an input clock terminal side and an output clock terminal side of the storage means; and a first switch circuit means for switching the first and second clock generation means between the input clock terminal side and the output clock terminal side of the storage means, and the variable filter means on the input side or output side of the storage means. G (including a second switch circuit means for switching, the first and second switch circuit means being connected to the input clock terminal side of the storage means for the first clock generation means in the first clock), and the second switch circuit means The clock generation means is connected to the output clock terminal side of the storage means, and the variable filter is connected to the input side of the storage means, so that the entire circuit is configured as a time axis compression/expansion circuit, and the circuit is in a second state. The first and second clock generation means are respectively connected to the output side and input clock terminal side of the storage means, and the variable filter means is connected to the output side of the storage means to form a frequency conversion circuit. An audio signal processing device characterized in that the audio signal processing device is configured to meet by switching connection so that.