JPS5831457A - Data processor - Google Patents

Abstract

PURPOSE:To easily detect a fault of a shift path, by inserting a logic collating flip-flop for taking a known logical value, into a known position in a shift path loop. CONSTITUTION:In case when a shift mode signal is not applied, in a logic ''1'' collating flip-flop with a shift function, status of logic ''1'' is held, and a logic ''0'' collating flip-flop 2 with a shift function always holds status of logic ''0''. N pieces of flip-flops 3 with a shift function, which are connected in order from an output of the logic ''0'' collating flip-flop 2 are used for a data register or a control signal, when the shift signal is not applied. A shift path checking circuit 5 collates a logical value prepared in advance with a data from the logic collating flip-flop, when the shift mode signal is generated, the number of times of shift is counted, and the number of times of shift reaches a prescribed value.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processor having a shift path, and in particular to a shift path data processor.

In devices with a conventional shift path, a method is often adopted in which the contents of the flip-flops (including registers) connected to the shift path are extracted and stored using the shift path. It was.

However, if a failure occurs in the 7th lip, 7th knob, etc. in the shift pass in a pigeon house using the 1st path, the contents of the 7th lip, 7a knob, etc. of the failed 7th lip and the 7th lip that were damaged after the failure will be disputed. There was a risk that it would turn out to be ``C, 1% theory, logic 1.''

On the other hand, by comparing the data of the shift pass &: R knowledge with the data generated by the shift pass, it was determined that the shift pass was malfunctioning.

However, this method has the drawback that when a large number of 79 and 7117 blocks are present in the shift path, the number of shifts between shifts becomes large and it takes a long time. mchi,
Schiff) There was a point where it was possible to judge whether there was a failure or a bud by just going around the loop of the path once. Therefore, the objective of the present invention is to insert a logical query Artub flop in the shift path to change the loop, and to create a shift path in the shift path. * By comparing the shifted out data with the data for MS, which corresponds to the shift fixed number C in advance, it is easy to see if there is a problem with the diad path and shift path. case,
And the shift path check for the first argument mjlsha 7ritsu 70tsubu glue 7toin input [11t- By connecting, l, y y) There is no failure by making the path go around once. Ichibasha &: are each 7 Ritubu Is the condition of the tubing within its original state? ! The purpose of this invention is to provide a new data 4611 device based on C4.

The above object of the present invention is to disconnect the input data bus when receiving the shift mode signal so that the output signal 1I14! ! A loop is formed by connecting the shift-in input between the 7-liff flops with the shift function and the output of the 7-rip-flop, respectively, to the shift-in input of the 7-rip-flop in the key stage. Shift path and at the start of shift always ``11@1'' (also,
is @0”) with a shift function! 111” (
Or "0") 70 knobs for inquiry and a logic m@o" (also Fi@1") with a shift function that always becomes logic m@o" (also Fi@1") at the start of a shift. The 79 and 70 knobs for logic verification are connected consecutively and meet within the loop of the shift path, and the first logic of the two logic verification 7V knobs is connected in series. 77) Pass &- pseudo-continuation to the shift-in input of the 7-flip 7w-tub for the master building, and when the data of the shift pass has completed one cycle, collate the data shifted out from the above-mentioned first theory 1 inquiry flip-flop bu. This is achieved by a data processing device having a shift path checker circuit that completes the process.

Next, let's talk about the good news! l! This will be explained in detail with reference to koji as an example.

*This is a block configuration showing an example of 1ma Honkomei.

11111cThhr, reference jll[I4!1 tlVy
) 4 - Given the F signal - temporary C is always logic 11
``Ljt with a shift function that maintains the state 11 @ 1'' query tree artsp, 2fll key note 7 sound tsubu foot tube 1 reverse, shift basket - IIJ) is not given - when the mine is not given m”o This is a logic with a shift function that maintains the state of ``s''.

-m@o” Verification flip 7- One flip 7 with shift function connected sequentially from the output of step 2
In order to keep the functions of the data II & control device in check when the shift signal is not given, the data register or the control II odd-period 7-lipf 11 can be used.

This is a shift path *** for forming a 4 & t shift path loop.

5 is shift) mode signal sales destination, shift) 1m number of callan F
And, when the number of shifts reaches a diagonal value, it is a shift path that has a function of comparing a pre-prepared logical value with 7 ribs, 7 W flops, or 60 data for logical inquiry.

In the above configuration, if the shift mode signal is generated and N+2W4 shift) is performed, it will go through one cycle, but the logic @ 0" verification flip 7W knob 2 has a shift function of 1 ahead. 7 rifbu 7-tsubu violence, v & is vy > If a failure occurs in path 4 and the data turns into lightning logic @ 1'', then C is,
Since the data of #+111■ is not logical @o' c t b, it is unfortunate that it cannot match the logic 10" data for N+1 Homare I that was previously published in V7 Topas Defuter 1Ils.

★Also, logic @11' 7 ribs for verification 70 logic beyond tube 1 @o'' Inquiry Flip Fuji tube 2 7 lip with shift function 7a If there is a failure in tube 5 or shift path 4, the data is always logical. @0″ pigeonhole, N+2I
Since the data of IIi does not become the logic @1", the shift bus check circuit 5 detects that it is consistent with the (N+2) 0 logic 11@1" data prepared in advance.

In this way, the data goes through one cycle with N+2- shifts, and if there is a failure, it is detected. If there is no failure, each 7 lip 7w
The content of the whelk returns to its true value.

If one shift path check circuit 5 is used to check the shift path loop of the augend, it is necessary to switch the connection to the shift path am and select the number of loops that the corresponding shift bus loop goes through. But, IFJCI! It can appear.

As explained above, in the present invention, by inserting a 79 hub for Ikkurihosha that takes a known value at a known position in the shift bus loop, failures in the shift path can be prevented. It has the effect of being detectable.

[Brief explanation of drawings]

FIG. 91 is a configuration diagram of a profiler showing an embodiment of the present invention. 1... Theory 11 @ 1'' Aritubu Arotsub for verification, 2...
・Archive flop for logic IlO" verification, 3... 7 rib flop with shift function, 4... Connection line for shift path, 5... Patent application for shift path checker circuit filed by NEC Co., Ltd.

Claims (1)

[Claims] When the shift mode signal is received, the input data bus is set to 1! II
Every time a taro tsuta occurs in #, set the output of the 7 lip 70 knob of II as the shift-in input.
: is always logic 11@1' (or 1o") - logic 11"l" (or @0") with shift function Company X 11”) Is it C? /7)1! Notsuke e-ron 11@o”
(51@1") IN combination 7'j"/bu 7a-7 and #
I distribute the output of each flip-flop in the previous stage to the shift-in input of each shift-in input of each flip-flop. ) Tsufu → − Tsubu,
A shift pulse that forms a closed loop with tttt in the slipper with a shift function, and the first connected dynamic of the 7 lip 7 w flop for checking the logic of the two keys that were encountered and connected. Pseudo-IIRtr is input to the shift-in input of the 7-lip 7-v knob for verification, and when the data on the shift bus goes through one cycle, the first & l: Connected theory! IIIA combined 7 rifubu 70 tsubu to shift door? ) A data control device characterized by having a shift path check circuit for checking the shift path and seven rive flops by comparing the stored data with logic verification data corresponding to the number of shifts in advance.