JPS583253A - Method of forming metal wiring on a semiconductor substrate - Google Patents

Abstract

PURPOSE:To improve the reproducibility of a wiring pattern by accumulating the first conductive layer of aluminum or aluminum alloy and the second conductive film of Ti or the like and continuously etching the first and second films in the same dry etching device with the resist as a mask. CONSTITUTION:The first conductive layer of aluminum or aluminum alloy and the second conductive layer of Ti, Mo, W, Ta or Nb or the like are continuously deposited on a substrate in a vacuum container to prevent the production of an Al2O3, a photoresist pattern is then formed, the second the first layers are then continuously plasma etched in a dry etching device, and the second layer remained on the pattern is removed, thereby forming an aluminum wiring pattern. In this manner, dead-time can be eliminated, an irregularity can be reduced, thereby improving the patterning accuracy and reproducibility.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a wiring pattern on a semiconductor substrate by dry etching a metal wiring film, particularly AA and At-based alloy spread.

Plasma etching of the film on the surface of the film is usually carried out using a parallel plate type device, and chlorine-based gas is mainly used as the etching gas. The etching rate varies due to the presence of the At, O, and thin films above.

When using 00t4 as etching gas, glow discharge causes cot4 +a-3oal, cypress+Ot*+2
The equilibrium state becomes #-, and the pure layer becomes At+GOj,
+; At0t, +O+・- and is etched,
The Ateas layer is At, O, -f-00t, +: 2
The reaction A I OL g + OO11- occurs,
It is believed that etching progresses. The Mut, 01
Etching with good reproducibility is not possible because the film thickness and film quality differ depending on the HT conditions and also vary slightly depending on the pace pressure of the dry etching equipment, residual gas concentration, etch gas pressure, power, distance between electrodes, etc. There is a major practical drawback that there is no such thing. In order to eliminate this instability, we created a spare room, At, O.

Efforts have been made to divide the etching conditions (gas pressure, power, etc.) between layers into two stages, or to change the etching gas composition, but perfect conditions have not yet been found. The current situation is that this is not the case.

The present invention improves the conventional At, 0. An improved technique was developed to reduce the variation in etching speed caused by the presence of layers.
This paper presents a dry etching method. Figure 1 shows
This is the cross-sectional shape before etching using the conventional method. In the figure, 1 is a phosphorus-doped oxide film, 2 is a copper or At-based alloy film, and 3 is a low-grade aluminum that is naturally formed on the surface of 2 in the atmosphere. 0. It is a membrane,
After forming the wiring pattern resist 4, dry etching is performed.

FIG. 2 is a correlation diagram between the etching time and the etching depth according to the conventional method. Under the same etching conditions,
Even after etching, the thickness is 1.0. The time spent etching the layer (DIIIL+1'l'1m5) is 5
As a result, variations in etch rate within a wafer, between wafers, and between batches become extremely poor. The present invention will be explained below with reference to examples.

In an example, FIG. 3 shows the cross-sectional shape before etching according to the present invention.
After continuous sputter deposition of the film tOμ and the T1 film 300X at the same time, a Z1370 resist nozzle pattern is formed. The structured wafer was etched using a parallel plate type reactive ion etching apparatus using C0t4 gas and 0.1 to α3 Torr's.
When continuous plasma etching was performed at 0.3 W/j, the etching was performed in a dead-time manner as shown in Fig. 4.
Etch rates with high reproducibility were obtained. (The T1 film remaining on the pattern was removed with a Hv:NHO,=1:10 solution to form a kl wiring pattern.

Example 2 As the first layer film, mul -81 (1%) -0u (0
5%), as the second layer film, 10001 Mo films were formed by continuous sputtering, and after patterning with AZ1570 resist,
When the first and second layer films were plasma-etched simultaneously using BCt-based etch gas, the same etch rate as in Example 1 was obtained, and no De & (ITime occurred. Also, the cross-sectional shape after etching was is shown in FIG. 5, and -Mo is At
Since the etch rate is high compared to the etch rate, the cross-sectional shoulder of the wafer becomes tapered, which has the advantage that the protective oxide film that will be deformed in the next process is less likely to crack.

<Residual Mo film was removed with 01F4 plasma after resist peeling> Example 3: First layer film was At 1μ, second layer film was W film so
o
5 [Use Lugist as a mask, first 01. After etching the W layer with a gas, the gas was switched to 00t4 and etching was performed, and a reproducible etch rate and pattern were obtained.

Example 4: Three Mb films were deposited on the kt-8i (1%) film as the first layer film.
001 was formed by continuous sputtering, and using AZ1350 resist as a mask, continuous dry etching was performed using 00t4 gas, and an etch rate and pattern with high reproducibility were obtained. Also T&
Similar results were obtained under similar conditions.゛As explained in the examples above, in the same vacuum vessel, Mo or Mo-based alloy, Ti, Mo, W, and a.

Mut, 0. Therefore, it is possible to form metal wiring on a semiconductor substrate by stable At dry etching without causing DsadTi.

[Brief explanation of drawings]

FIG. 1 shows the cross-sectional shape before the conventional method of dry etching. FIG. 2 is a diagram showing the relationship between etching time and etching film thickness in Mutt dry etching according to a conventional method. Figure 3 shows the cross-sectional shape before dry etching according to the present invention;
The figure is a diagram showing the relationship between etching time and etching film thickness. FIG. 5 shows the cross-sectional shape of At after etching and resist peeling according to the method of the present invention. 1...phosphorus-doped oxide film 2...mu or At-based gold film 3...mu t, 0. Film 4...Resist mask 5-...D@h6 Tim5 6・"""'l"t"jNblTa gold 11s or more Applicant Kinsha Suwa Seikosha Co., Ltd. Agent Patent attorney Tsutomu Mogami Fig. 1 Fig. 2 Kuiko v+frflJ! Fig. 5

Claims (1)

[Claims] A first layer semiconductor film made of a Ti-based alloy or a Ti-based alloy;
, Mo , W, T & , Mb (1) Izureka Yori Naru 2nd
A step of successively debossing the layer conductor film in the same vacuum container, a photo step of forming a wiring pattern resist, and a second and first conductor film using the resist F as a mask in the same dry etching device. , a method for forming metal wiring on a semiconductor substrate, characterized by continuous plasma etching.