JPS583303A - phase detection circuit - Google Patents

Abstract

PURPOSE:To form a phase detecting circuit for microwave signals with high sensitivity and stability, by using a multigate field effect transistor. CONSTITUTION:Signal input lines 12 and 13 are connected respectively to gates G1 and G2 of a DGFET11. The lines 12 and 13 are selected so that the microwave input signals S1 and S2 can have a phase difference of pi/2. The source of the DGFET is grounded as high frequencies and grounded as DC via a bias resistor 18. A specified bias current flows to a power supply +B to the resistor 18. The drain D of the DGFET is connected to the power supply via a load 24 and an output in response to the phase difference of the signals S1 and S2 is obtained from the load 24. Thus, the value of the resistor 18 is selected smaller to increase the detection sensitivity and the DGFET increases the stability of detecting operation. Thus, a microwave signal phase detection circuit with high sensitivity and stability can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase detection circuit suitable for detecting the phase of a microwave signal, and more specifically, the present invention relates to a phase detection circuit suitable for detecting the phase of a microwave signal. The purpose of the present invention is to provide a phase detection circuit suitable for detecting the phase of wave signals. 1. In FIG. 1, l and ko are microstrip threat paths, respectively, and their respective input ends /a and 2a are
Microwave signals S/ and S2 are supplied from. Each of the lines l and l is connected to a wavelength branch line directional coupler 3, whose output terminals q and 1 are grounded via diodes 6 and 7, respectively, which are oriented in opposite directions. Then, the cathode of diode B and the anode of diode 7 are commonly connected, and a
The output terminal 10 is grounded through the cross section and the load resistor 9, and the output terminal 10 is derived from the connection point between the inductor 7 and the load resistor 9.3. and propagates to the output end S via the branch lines 3C and 3b or 3a and 3d, each having the same wavelength length <l/lI, with a mutual phase difference of π/2. Further, the microwave signal S2 from the input end 2a is also transmitted from the line λ to the output end Ta via the branch line 3b of the directional coupler 3, and the branch lines 3C and 3a or 3b and 3d.
are propagated to the output terminal q through the respective channels with a mutual phase difference of π/2.

Each microwave signal propagated to these output terminals /IL and S is detected by the diode 6 and the detection outputs from both diodes 6 and 7 are combined, and the output terminals /IL and 2a are combined.
A phase detection output corresponding to the mutual phase difference of the microwave signals S/ and S2 supplied to the output terminal 10 is obtained at the output terminal 10.

In such conventional phase detection circuits for microwave signals, the phase detection section is formed by a pair of diodes, which has the disadvantage of low detection sensitivity. The reflection characteristics for the input and the temperature characteristics of the microwave signal input vs. DC output characteristics change depending on the input power of the input microwave signal, but these characteristic changes can be balanced between the λ diodes used in the pair. Since it is difficult to detect the phase, there is also a drawback that the phase detection operation lacks stability.

SUMMARY OF THE INVENTION Therefore, the present invention provides a novel phase detection circuit suitable for detecting the phase of a microwave signal, which is constructed using a multi-gate field effect transistor and can eliminate the drawbacks of conventional phase detection circuits. , also discloses a novel frequency discrimination circuit in which such a phase detection circuit is adapted. Embodiments and application examples of the present invention will be described below with reference to FIG. 2 and subsequent drawings.

FIG. 2 shows an example of a phase detection circuit according to the present invention. ///
is a multiple gate field effect transistor (hereinafter referred to as DG-FE)
T) has two gates, a first gate electrode and a second gate electrode, a source and a drain, respectively.
Microstrip lines 12 and 13 for signal input are respectively connected to the first gate electrode G/ and the second gate electrode G2 from which the second gate electrode G2, source electrode S and drain/electrode G2 are derived. Connected. These lines /2 and /3 are DC grounded via high-frequency blocking inductors /9 and /9, and the respective input terminals /2a and /2a and /2a, ? a, respectively, the microwave signals S' and S2
is supplied. Here, the length from the input end /2a of the line 12 to the first gate electrode G is the input end /3 of the line 13.
The length from a to the second gate electrode G2 is an odd multiple of //41 of the propagation wavelength λg (21m (2n+/),
n = θ, /X 2.3...). Therefore 1. The microwave signals S/ and S2 supplied to the input terminals /ja and /3a are respectively connected to the first gate electrode Gl.
And while propagating to the second gate electrode G2, the microwave signal S/ is an odd number multiple of π/2 (π/2・(2n+/), n=01/, ko, 3 °”°
They have a mutual phase difference of ゛). DG・FET1t
The source electrode S has an odd multiple of l/lI of the propagation wavelength chain (
λg/su・(,2n+/), n=O,/, ko1
．． 7.・, , , ) length of open micros) I
A J-tube line 16 is connected to the high-frequency ground state, and is also grounded via a high-frequency blocking inductor/suction 17 and a bias resistor/g. A bias current supply variable resistor 19 is connected between one end of this bias resistor /g and the power supply -1'B. Furthermore, DG-
A microstrip line 20 is connected to the drain electrode of the FET//, and a termination resistor 22 is connected to the end of the wire via a DC blocking switch 21 for high frequency matching termination. Reflections are prevented. The line 2o is connected to a power source 1B via a high frequency/blocking I/D circuit 23 and a load resistor 2q. An output terminal 2s is led out from a connection point between the inductor/suction 23 and the load resistance 2q.

The phase detection circuit shown in FIG. 2 and constructed in this manner is represented in terms of a DC equivalent circuit as shown in FIG. 3.゛Here, D'G-FE'l'// is its source electrode S
Due to the voltage drop caused by the current flowing through the bias resistor/g connected to the gate, an operating gate bias voltage is applied that makes the gate negative with respect to the source (the gate potential is lower than the source potential), and the bias is set near the pinch-off voltage. is activated to cause a change in the drain/current corresponding to a change in the high frequency input supplied to the first gate electrode Gl and the second gate electrode G2, and the load resistance 2hi caused by this change in drain/current is An output can be obtained at the output terminal 2S even when the voltage at both ends changes.

In this case, in order to increase the ratio of the output change to the high frequency input change, that is, to increase the sensitivity of the circuit, the DG-FET// source electrode S is connected to the The resistance value of the bias resistor/g is set to be as small as possible. However, if the resistance value of the bias resistor /g is small, the current If flowing out from the source of the DG-FET /'/ whose bias is set near the pinch-off voltage is small, so this current flows through the bias resistor /g. It is not possible to obtain the necessary gate bias voltage by simply flowing through g. Therefore, bias is applied from the current 1B through the bias current supply variable resistor connected between one end of the bias resistor 1g and the power supply 1B.

An additional bias current p is poured into the resistor /g, and the necessary gate bias voltage is obtained by the current flow f and p of both currents.1 This additional bias current Ip is applied to the bias current supply variable resistor 19-, the predetermined value is adjusted to 70 times or more of If. As a result, it is possible to increase the sensitivity of the circuit by reducing the resistance value of the bias resistor /g connected to the source electrode S of the DG FET //, and to obtain the necessary gate bias voltage by this bias resistor /g. are compatible.

The above-mentioned DG-FET// has two gate electrodes, the first and second gate electrodes, but the DC-FE'T has two single gate field effect electrodes, as shown in Figure qA. It can be considered that transistors/transistors (hereinafter simply referred to as FETs) 26 and 27 are connected with their drain-source paths connected in series. Then, as shown in FIG.
If the source electrode of 7 is S, and the drain electrode of FET2A is D, this represents DG-FET// with equal constraints, and the input terminal /2 is connected to the gate electrode G and G2, respectively.
a and/or? The circuit shown in Figure B, in which the source electrode S is grounded, and a load resistor 2tI is connected to the drain/electrode, is a high-frequency equivalent circuit representation of the phase detection circuit shown in Figure 2. be.

In the circuit shown in FIG. : Drain of FET2?
The source voltage is Vd, the drain current of FET z6 is 1 dls, and the drain current of FET 27 is id2.

As mentioned above, the gate bias voltage of DG-FET// is set close to the pinch voltage type, so FET
The gate bias voltage of ET2A and ET27 is also set near the pinch-off voltage. In general, F.E.
When the gate-source voltage is around the p/thio7 voltage V, the relationship between the gate-source voltage VQ and the drain/current iD is jD=α(Vp k-vc)
, (where α and k are constants) holds true. Therefore, in FIG.
Voltage) = α(Vpl-kl・(v'g/-Vd2.)H...
...(/,) holds true 1, where Vd, 2 is the function of 7g2 F(
If the higher-order terms regarding 7g2 are omitted, then Vd2 = aVg2 (where a is a constant)...-
(,2).

It can be expressed as Substituting equation (2) into equation (1) and expanding, 1dt=α(Vpl kl ” C'j'gt a
VH2) l'2=α(V/'2Vp/
” kl (V' g / a VH2) ten k12
・v'gl ko2a・k111v'g/・7g20/
'2#a2・VH22)°°°°°Mountain/Mountain°゛(3).

Here, v'gl and V g 2 are voltage values when the microwave signals S/ and S2 supplied to the input terminals /Ja and /3a are applied to the first gate electrode Gl and the second gate electrode G2, respectively. It is. Now the microwave signals Sl and S2
Assuming that there is a phase difference θ between the , as mentioned above, Sl is further π/2 with respect to S2
Odd multiple of (π/2・(,2T1+/, n=o, t,;L
, 3=), so v'g7=cos (ωt+θ+π/2− (2n+/
))=cos(ωt+φ), (where φ=θ+π/2・
(2n+l)) ・・・・・・・・・・・・・・・(
tI) Vg2=cosωt −0==== (!;
). Substituting equations (4=) and (Yu) into equation (3,) and taking the time average idl of idl, the high frequency term in equation (3) becomes zero, so 1(1(=α( Vpl2-?2a11kl@C08(ω
t+φ)・e08ωt) = α(Vp12=a * kl* (cos (!ωt
+φ)+, and since C03 (2ω = 1φ) is also zero when averaged by twice the high and dark wave term, 1 cos α (VP/co a * k7 a cosφ), φ=θ+π/ 2. Since (2n+/), 1al
=α(Vl)/2-aakl*sinθ). That is, idl is the DC term and the microwave signals S/ and S2
consists of the difference between the term and the term that changes depending on the phase difference θ between the
It is an odd function with respect to θ.

The output V available at the output terminal 25 of the circuit shown in FIGS. 2 and 3. If the voltage of power supply element B is ve, then the voltage generated from the power supply voltage VB to the drain current of DG-FETll, that is, the time average of the FET26ρ drain/current idl in Figure q B, and the load resistance voltage is Because it is obtained by subtracting the drop: power supply voltage VB and FET2
It is expressed as the difference between the time average of the drain/current idl of & and the product of the load resistance - the resistance value R of
Vpl) +α@a a k/*sinθ. Therefore, the output vo obtained at the output terminal 2S is
This output V is an odd function with respect to the phase path θ between the microwave signals S/ and S2. is the DC voltage that changes according to the change in the phase difference θ, that is, in this case, the microwave signal S
This is a phase detection output obtained by detecting the phase of the microwave signal S/ with respect to the phase of S/2.

Based on the above, the circuit shown in FIG. 2 has input terminals /Ja and /, ? It can be seen that the circuit operates as a phase detection circuit, in which an output corresponding to the phase difference between the microwave signals S-/ and S2 supplied to the terminals a is obtained at the output terminal.

In this case, as mentioned above, the source electrode S of DG-FETll
By selecting the resistance value of the bias abrasive resistor LZ connected to the bias grinding resistor 1 to be as small as possible, the output V with respect to the change in the phase difference θ, that is, the change in the input. The ratio of change in is considered to be large, and therefore high phase detection sensitivity is obtained. In addition, since the first and second gates of DG/FETll, which is the phase detection section to which microwave signal input is supplied, are formed at positions extremely close to each other on the same semiconductor chip, various There is almost no difference in characteristics, and the stability of the phase detection operation is maintained extremely well.

FIG. S shows a frequency discrimination circuit constructed by applying an example of the phase detection circuit according to the present invention shown in FIG. 2 above. In FIG. S, 2g indicates the entire phase detection circuit shown in FIG. 2, and each part is given the same number as in FIG. 2, and detailed explanation thereof will be omitted.

Microstrip lines 9 and 30 are integrally connected to the input terminals /Ja, U, and 13a of this phase detection circuit 2g, respectively. And the resonant frequency is f.

(For example, //, AAGH2) dielectric resonator 31
are arranged to couple these two microstrip lines to each other. One end of the microstrip line 29 is an input end 29a, from which an input microwave signal -8 whose frequency f8 is centered at (o, = tt, 44 GHz and varies by ±7θMHz7ω) is input.
3 is supplied. In this case, the propagation wavelength λg of the phase detection circuit 2g is, for example, the frequency f. The wavelength for the wavelength is selected.

In such a configuration, input microwave signal S3 is connected to line 2.
When the signal is supplied to the input end 29a of the phase detection circuit 29, the signal is supplied to one input end (2a) of the phase detection circuit 2g connected to the line 29 through the coupling part between the line 2q and the dielectric resonator 31.
The line 3 via the coupling part between the line 30 and the dielectric resonator 3/
0 and reaches the other input terminal /, 7a of the phase detection circuit 2g connected to the line 30. At this time, the input terminal /,
The number reaching 2a does not change and is fs, but its phase is S3
are assumed to have changed in opposite ways to each other by a phase amount corresponding to the frequency f8. That is, the frequency f3 of S'3 passing through the coupling portion between the line 2q and the dielectric resonator 31 is the resonant frequency f of the dielectric resonator 31. When it is the same as , the phase does not change with respect to the phase of S3, but f8 is f. When it is lower, the phase advances with respect to the phase of S3, and fB is f. When it is higher than that, the phase is delayed with respect to the phase of S3, and the phase change is ±π/
In the range of 2, fs and f. It depends on the difference between

If this situation is illustrated with the frequency f8 on the horizontal axis and the phase change ψ with respect to S3 on the vertical axis, the solid line in FIG. When the frequency fs of the incoming S″3 is the same as f, the phase does not change with respect to the phase of S3, but ζ
When fs is lower than fo, the phase lags behind the phase of S3.

Also, f8 is f. When it is higher, the phase advances with respect to the phase of S3, and the phase change is within the range of ±π/2, and f
It depends on the difference between s and fo.

If this is shown with the frequency fs on the horizontal axis and the phase change ψ with respect to 'S3 on the vertical axis, it will become as shown by the broken line in FIG. 6. From this, S′3 and S″3 are fs=f
With o as the center frequency, there is a mutual phase difference θ' corresponding to fs.

This means that the input terminals /, 2a and 7 of the phase detection circuit
3 & are supplied with microwave signals s'3 and S''3 whose mutual phase difference is the phase difference θ' that changes according to the change in the frequency fs of the input microwave signal S3, and the phase detection circuit 2g. At the output terminal, an output V'o corresponding to the phase difference θ' is obtained by the operation explained in the circuit shown in FIG. ', i.e., the frequency f of the input microwave signal s3
8, and the entire circuit shown in FIG. 5 constitutes a frequency discrimination circuit 1. In this case, the input terminals /2a and /, ? of the phase detection circuit 2g. al
'rThe supplied microwave signals s'3 and S'3 change in frequency, and the frequency change is, for example, a force tOMH centered around f o = //j6 GHz.
z, the influence of the change in the length of the //q wavelength due to this frequency change on the circuit configuration of the phase detection circuit 2g can be substantially ignored.

FIG. 7 shows a portion of another example of the phase detection circuit according to the present invention. In this example, parts corresponding to the columns shown in FIG. 2 are given the same numbers as in FIG. 2 and their explanations are omitted, but the bias current supply in the columns shown in FIG. In place of the variable resistor /9, a transistor 32 is used with its emitter connected to one end of the bias resistor /g and its collector connected to the power supply 1B. This transistor 32 has an emitter follower type toner, and in order to supply current to the bias resistor (g), the bias resistor (g) connected to its emitter has a potential VS at one end approximately equal to the base of the transistor 32 (VbK). determined, DG-F
The change in v8 due to the change in the source current of ET// is small. This means that the resistance value of the bias resistor/g is isometrically smaller, and the sensitivity of the circuit is improved. Furthermore, by temperature-controlling the pace potential vb of the transistor 3λ, for example, it is possible to compensate for the temperature of the output obtained at the output terminal 2.

In each of the above-mentioned columns, the DC blocking capacitor 21 and the terminating resistor 22 used at the end of the line 2o connected to the drain electrode of the DC-FET// are, for example,
It is convenient for the circuit configuration to use a capacitor/resistance integrated component 33 configured as shown in the figure. Figure g A
In this example, a silicon low resistance layer 35 is formed on one surface of a silicon substrate 3q, an insulating layer 3A made of silicon oxide is formed thereon, and a pair of electrode metal layers 3A is further formed on that.
7a and 37b are formed.

In this case 9, the electrode metal layer 37a and 7? A conductor is formed between the silicon low-resistance layer 3S and the silicon low-resistance layer 3S, and a resistance is formed between the electrode metal layers of the silicon low-resistance layer 3S. Then, for example, the electrode metal layer J7a is
0, the electrode metal layer 37b is grounded and used, and the capacitor formed between the electrode metal layer 37 & 37b and the silicon low resistance layer 35 becomes a DC blocking capacitor 2/, and the silicon The resistance between the metal layers for both electrodes of the low resistance layer 3S becomes two terminating resistors.

In the example shown in FIG. B, in place of the silicon low resistance layer 3S in the example shown in FIG. 3g to create a resistor, and the rest is the same as the example in Fig. 3A.

In order to obtain the desired capacitance value in these integrated parts of the capacitor/resistor, the metal layer for the electrode, ? ? a and 37b
It is sufficient to select the area of the silicon oxide insulating layer 36 and the thickness of the silicon oxide insulating layer 36. However, in order to obtain the desired amount of resistance, it is necessary to select the dimensions of the area between the metal layers for both electrodes of the silicon low resistance layer 3S or the metal resistance film 3g. do it.

As explained above, in the phase detection circuit according to the present invention, the phase detection section is composed of a DG-FET which is an active element, and the resistance value of the The phase detection sensitivity is extremely high because the phase detection sensitivity is extremely high.The two gates to which the input microwave signals to be phase-detected are supplied are formed very close to each other on the same semiconductor chip. Since the various characteristics are the same, extremely stable operation can be obtained.Also, in the case of microwave signal phase detection, if the phase detection section is constructed with a diode as in the past, the diode The reflection characteristics for microwave signal input change depending on the input power of the input microwave signal, but since DG=-FET is used in the present invention, the reflection characteristics for microwave signal input change depending on the input power. There is also the advantage that there is almost no dependence, making it easy to design the input matching circuit.Furthermore, since there is no need for a //II wavelength branch line directional coupler, etc., the overall configuration can be made smaller. It is a characteristic.

Note that the present invention is not limited to the above-mentioned embodiments,
Of course, various configurations may be adopted without departing from the gist of the invention.

[Brief explanation of the drawing]

Fig. 1 is a circuit connection diagram showing a conventional phase detection circuit for microwave signals, Fig. 2 is a circuit connection diagram showing an example of a phase detection circuit according to the present invention, and Figs. 5 is a circuit connection diagram showing a frequency discrimination circuit constructed by applying an example of the phase detection circuit according to the present invention; FIG. 6 is an equivalent circuit diagram used to explain the phase detection circuit shown in FIG. FIG. 7 is a diagram for explaining the frequency discrimination circuit shown in Book (21). A circuit connection diagram partially showing another example of the phase detection circuit according to the invention, FIG. 3 is according to the present invention. FIG. 2 is a perspective view showing the components that may be used to construct a portion of the phase detection circuit. In the figure, 11 ko, /, lX'/3.16.20X 2
9 and 30 are microstrip lines, 3 is //'I wavelength branch line directional coupler, /l is a multi-gate x field effect transistor (DG-FE'T), l is a bias resistor, and 19 is a bias current Supply variable resistor, t is load resistance, 26 and 27 are single gate field effect transistors, 3
1 is a dielectric resonator, 32 is a transistor, and 33 is a capacitor/resistance integrated component.

Claims (1)

[Claims] Incoming power, first and second high frequency signal input lines are connected to the first and second gates of the multi-gate field effect transistor, and the first and second lines are connected from their input ends. While reaching the above-mentioned first and second gates, one of the first and second input signals from each input terminal is π// with respect to the other π.
The field effect transistor is selected to have a phase difference of an odd multiple of 2, and the source of the field effect transistor is grounded in terms of high frequency and grounded in terms of direct current via a bias resistor, and the source of the field effect transistor is connected to the bias resistor from the power source. A predetermined bias current is supplied, and the drain of the field effect transistor is connected to a power supply via a load, and the drain of the field effect transistor is connected to a power source through a load, and the bias current is supplied to the input terminals of the first and second lines, respectively. and a second input signal, the phase detection circuit is configured to obtain an output corresponding to the phase difference between the input signals even when the voltage at the load changes.