JPS5833112B2 - Kiroku house - Google Patents

Kiroku house

Info

Publication number
JPS5833112B2
JPS5833112B2 JP50028844A JP2884475A JPS5833112B2 JP S5833112 B2 JPS5833112 B2 JP S5833112B2 JP 50028844 A JP50028844 A JP 50028844A JP 2884475 A JP2884475 A JP 2884475A JP S5833112 B2 JPS5833112 B2 JP S5833112B2
Authority
JP
Japan
Prior art keywords
recording
voltage
electrode
electrodes
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP50028844A
Other languages
Japanese (ja)
Other versions
JPS51103733A (en
Inventor
睦夫 小川
登 村山
則定 竹内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP50028844A priority Critical patent/JPS5833112B2/en
Publication of JPS51103733A publication Critical patent/JPS51103733A/ja
Publication of JPS5833112B2 publication Critical patent/JPS5833112B2/en
Expired legal-status Critical Current

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  • Dot-Matrix Printers And Others (AREA)
  • Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
  • Electrophotography Using Other Than Carlson'S Method (AREA)
  • Fax Reproducing Arrangements (AREA)

Description

【発明の詳細な説明】 本発明は複数の記録電極及び複数の対電極を用い記録電
極の電圧と対電極の電圧とを相加的に記録媒体に作用さ
せて記録を行う記録装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a recording device that performs recording by using a plurality of recording electrodes and a plurality of counter electrodes and applying the voltage of the recording electrode and the voltage of the counter electrode additively to a recording medium.

従来、この種の記録装置としては第1図に示すような静
電記録装置がある。
Conventionally, as this type of recording apparatus, there is an electrostatic recording apparatus as shown in FIG.

すなわち、複数の記録電極1□〜1m、2.〜2m、・
・・n1〜nmは対電極11□〜11nと対向させて一
列に配置されるが、駆動回路の数を減少させるために複
数の電極列に等分されて各電極列共通に駆動回路12□
〜12mに接続される。
That is, a plurality of recording electrodes 1□ to 1 m, 2. ~2m,・
...n1 to nm are arranged in a line facing the counter electrodes 11□ to 11n, but in order to reduce the number of drive circuits, they are equally divided into a plurality of electrode rows, and each electrode row has a common drive circuit 12□.
Connected to ~12m.

複数の対電極111〜11nは複数の記録電極11〜i
mt・・・n1〜nmに対してその電極列毎に記録媒体
を介して対向し、それぞれ駆動回路131〜13nに接
続される。
The plurality of counter electrodes 111-11n are the plurality of recording electrodes 11-i.
mt . . . n1 to nm, each of the electrode rows faces each other via a recording medium, and is connected to drive circuits 131 to 13n, respectively.

この駆動回路13、〜13nはそれぞれトランジスタT
R1、抵抗R1〜R4よりなり、通常、入力電圧により
トランジスタTR1が導通して対電極に対する駆動電圧
を0となし、入力パルスによりトランジスタTR,が不
導通になると、対電極に対する駆動電圧を電源電圧+E
にする。
These drive circuits 13, to 13n each have a transistor T
R1, and resistors R1 to R4. Normally, when the input voltage makes the transistor TR1 conductive, the driving voltage to the counter electrode becomes 0. When the input pulse makes the transistor TR non-conducting, the driving voltage to the counter electrode becomes the power supply voltage. +E
Make it.

駆動回路131〜13nは入力パルスが順次加えられて
対電極111〜11nに順次電源電圧+Eを加えて走査
する。
Input pulses are sequentially applied to the drive circuits 131 to 13n, and a power supply voltage +E is sequentially applied to the counter electrodes 111 to 11n for scanning.

駆動回路121〜12mはそれぞれ入力回路保護用定電
圧ダイオードZD及びカップリングコンデンサC1より
なるレベルシック、トランジスタTR2及び抵抗R5〜
R7よりなり、通常トランジスタTR2が不導通で記録
電極の電圧をOとし、入力信号によりトランジスタTR
2が導通ずると、記録電極に電源電圧−Eを加える。
Each of the drive circuits 121 to 12m is a level chic circuit consisting of a constant voltage diode ZD for input circuit protection and a coupling capacitor C1, a transistor TR2, and a resistor R5 to
Normally, the transistor TR2 is non-conducting and the voltage of the recording electrode is set to O, and the input signal causes the transistor TR
When 2 becomes conductive, a power supply voltage -E is applied to the recording electrode.

記録媒体は記録電極に電源電圧−Eが加えられると同時
に対電極に電源電圧子Eが加えられて2Eが印加された
ときにのみその印加部分に静電潜像が形成される。
In the recording medium, an electrostatic latent image is formed in the area where the recording electrode is applied only when the power supply voltage -E is applied to the recording electrode and the power supply voltage E is applied to the counter electrode at the same time and 2E is applied.

この記録媒体は記録電極11〜nm、対電極11□〜1
1nの配列方向と直角な方向に移動させられながら静電
潜像が1ラインづつ順次形成され、この静電潜像が現像
されることにより記録が行われる。
This recording medium has a recording electrode of 11 nm and a counter electrode of 11□ to 1 nm.
An electrostatic latent image is sequentially formed line by line while being moved in a direction perpendicular to the 1n arrangement direction, and recording is performed by developing this electrostatic latent image.

しかし、このような記録装置にあっては駆動回路121
〜12m、13.〜13nに互に異極性の二系統の電源
が必要になって電源が複雑化し、かつ駆動回路12□〜
12mの入力段にレベルシフタを必要とし回路が複雑に
なる。
However, in such a recording device, the drive circuit 121
~12m, 13. ~13n requires two power supplies with different polarities, which complicates the power supply, and the drive circuit 12□~
A level shifter is required at the 12 m input stage, making the circuit complicated.

そこで、第2図に示すように、駆動回路13□〜13n
の電源電圧を+2Eとし、かつ駆動回路121〜12m
の電源電圧を+2Eとすると共にレベルシフタを除き、
通常、トランジスタTR2を不導通にし入力信号により
トランジスタTR2を導通させるようにしたものがある
Therefore, as shown in FIG. 2, drive circuits 13□ to 13n
The power supply voltage is +2E, and the drive circuit 121 to 12m
The power supply voltage is set to +2E, and the level shifter is removed.
Generally, there is a device in which the transistor TR2 is made non-conductive and the transistor TR2 is made conductive by an input signal.

このような記録装置によれば電源は1系統でよくなり簡
単化されると共にレベルシックがT4 になって回路が
簡単になる。
According to such a recording device, only one power supply system is required, which simplifies the system, and the level chicness becomes T4, which simplifies the circuit.

しかし、記録電極相互間及び対電極相互間の耐電圧は2
E以上心要となり製造上問題がある。
However, the withstand voltage between the recording electrodes and between the counter electrodes is 2
E or higher is critical and there is a manufacturing problem.

又電源は高圧になるので種種の困難な問題を生ずる。Also, the high voltage power supplies present a variety of difficult problems.

本発明は上記のような欠点を除去し、電源の簡単化及び
回路の簡単化を図ることができるばかりでなく電源を低
圧化して各電極間の耐圧を低くすることができる記録装
置を提供しようとするものである。
The present invention aims to eliminate the above-mentioned drawbacks and provide a recording device that can not only simplify the power supply and circuit, but also lower the voltage of the power supply and reduce the withstand voltage between each electrode. That is.

以下図面を参照しながら本発明の一実施例について説明
する。
An embodiment of the present invention will be described below with reference to the drawings.

第3図に示すように、複数の記録電極21.〜21 m
、 221〜22m・・・2n1〜2nmは対電極3
1、〜31nと対向させて一列に配置され、かつ複数の
電極列に等分されて各電極列共通に駆動回路321〜3
2mにそれぞれ接続される。
As shown in FIG. 3, a plurality of recording electrodes 21. ~21 m
, 221~22m...2n1~2nm is the counter electrode 3
Drive circuits 321 to 3 are arranged in a line facing the electrodes 321 to 31n, and are equally divided into a plurality of electrode rows, and are common to each electrode row.
2m each.

複数の対電極31.〜31nは複数の記録電極211〜
2nmに対してその電板列毎に記録媒体を介して対向す
るように配置され、それぞれ駆動回路33、〜33 に
接続される。
A plurality of counter electrodes 31. ~31n is a plurality of recording electrodes 211~
2 nm, each electrode plate row is arranged to face each other with a recording medium interposed therebetween, and is connected to drive circuits 33, to 33, respectively.

この駆動回路33.〜33nはそれぞれNPN形トラン
ジスタTR3、抵拐ls〜R1□及びコンデンサC2よ
りなり、トランジスタTR3のベースは入力抵抗R8を
介して入力端子に接続されると共に接地点との間にノく
イアス用抵抗R9が接続される。
This drive circuit 33. ~33n are each composed of an NPN transistor TR3, a resistor Is~R1□, and a capacitor C2, and the base of the transistor TR3 is connected to the input terminal via an input resistor R8, and is connected to the ground by a resistor for earthing. R9 is connected.

トランジスタTR3のエミッタは接地され、トランジス
タTR3のコレクタがコレクタ抵抗R1oを介して正の
直流電源〈+E〉に接続される。
The emitter of the transistor TR3 is grounded, and the collector of the transistor TR3 is connected to a positive DC power supply <+E> via a collector resistor R1o.

又トランジスタTR3のコレクタが抵抗R1□、コンデ
ンサC2及び抵抗R12を直列に介して直流電源〈+E
〉に接続されコンデンサC2及び抵抗R12の接続点が
対電極に接続される。
In addition, the collector of the transistor TR3 is connected to the DC power supply 〈+E
), and the connection point of capacitor C2 and resistor R12 is connected to the counter electrode.

コンデンサC2及び抵抗R12は微分回路を構成し、抵
抗R71は微分回路からトランジスタTR3への突入電
流を減少させるためのものである。
Capacitor C2 and resistor R12 constitute a differentiating circuit, and resistor R71 is for reducing rush current from the differentiating circuit to transistor TR3.

駆動回配32□〜32mはNPN形トランンジスタTR
4及び抵抗R13〜R15よりなり、トランジスタTR
,のベースは入力抵抗R13を介して入力端子に接続さ
れると共に接地点との間にバイアス用抵抗R14が接続
される。
Drive circuits 32□ to 32m are NPN transistors TR
4 and resistors R13 to R15, and the transistor TR
, is connected to the input terminal via an input resistor R13, and a bias resistor R14 is connected between the base and the ground point.

トランジスタTR4のコレクタはコレクタ抵抗R15を
介して直流電源〈+E〉に接続されると共に記録電極に
接続される。
The collector of the transistor TR4 is connected to a DC power supply <+E> via a collector resistor R15, and is also connected to a recording electrode.

駆動回路33□〜33nは通常、入力電圧が0でトラン
ジスタTR3が導通し電源電圧く+E〉を抵抗R12を
介して対電極に加える。
In the drive circuits 33□ to 33n, normally, when the input voltage is 0, the transistor TR3 is turned on and the power supply voltage +E> is applied to the counter electrode via the resistor R12.

このとき、コンデンサC2は電源電圧く+E〉まで充電
される。
At this time, the capacitor C2 is charged to the power supply voltage +E>.

負の入力パルスによりトランジスタTR3が不導通にな
ると、コンデンサC2の充電々荷が対電極に放電され対
電極の電圧が電源電圧〈+E〉の2倍<+2E>になる
When transistor TR3 becomes non-conductive due to a negative input pulse, the charge in capacitor C2 is discharged to the counter electrode, and the voltage at the counter electrode becomes twice <+2E> than the power supply voltage <+E>.

駆動回路331〜33nは入力パルスが順次加えられて
対電極31、〜31nの電圧を+Eから+2Eに順次し
走査を行つO 駆動回路321〜32mは通常、入力電圧がOでトラン
ジスタTR4が不導通となり電源電圧〈+E〉を記録電
極に加える。
The drive circuits 331 to 33n perform scanning by sequentially applying input pulses to the counter electrodes 31 and 31n from +E to +2E. It becomes conductive and a power supply voltage <+E> is applied to the recording electrode.

正の入力信号によりトランジスタTR4が導通ずると、
記録電極の電圧をOにする駆動回路321〜32mは入
力信号が駆動回路331〜33nの入力パルスよりm倍
のタイミングで順次加えられる。
When transistor TR4 becomes conductive due to a positive input signal,
Input signals are sequentially applied to the drive circuits 321 to 32m that set the voltage of the recording electrodes to O at a timing m times the input pulse of the drive circuits 331 to 33n.

そして記録媒体は記録電極の電圧がOになると同時に対
電極の電圧が+2Eになったときにその電極間の部分に
のみ荷電されて静電潜像が形成される。
Then, when the voltage of the recording electrode becomes O and at the same time the voltage of the counter electrode becomes +2E, the recording medium is charged only in the area between the electrodes, and an electrostatic latent image is formed.

この記録媒体は駆動装置により記録電極211〜2nm
及び対電極31□〜31nの配列方向と直角な方向に移
動させられながら静電潜像が1ラインづつ順次形成され
、この静電潜像が現像装置により現像される。
This recording medium has a recording electrode of 211 to 2 nm by a driving device.
While being moved in a direction perpendicular to the arrangement direction of the counter electrodes 31□ to 31n, an electrostatic latent image is sequentially formed line by line, and this electrostatic latent image is developed by a developing device.

第4図は本発明の他の実施例であり、第3図において抵
抗R12と並列にダイオードDを接続したものである。
FIG. 4 shows another embodiment of the present invention, in which a diode D is connected in parallel with the resistor R12 in FIG.

このダイオードDはコンデンサC2及び抵抗R72より
なる微分回路の出力のうち負の成分を除去し、かつ電源
投入時における対電極の電圧の立上りを改善するように
動作する。
This diode D operates to remove a negative component from the output of the differentiating circuit composed of the capacitor C2 and the resistor R72, and to improve the rise of the voltage at the counter electrode when the power is turned on.

駆動回路33、〜33nの入力パルス幅に対して駆動回
路321〜32mの入力信号の周期が極めて太きいとき
にはダイオードDを省略して抵抗R12の値を大きく設
定し微分回路の時定数を大きくして微分出力のうちの負
成分を除去することができる。
When the period of the input signal of the drive circuits 321 to 32m is extremely large compared to the input pulse width of the drive circuits 33 and 33n, the diode D is omitted and the value of the resistor R12 is set to a large value to increase the time constant of the differentiating circuit. The negative component of the differential output can be removed by

なお、本発明は上記実施例に限定されるものではなく、
要旨を変更しない範囲で種々に変形して実施することが
できる。
Note that the present invention is not limited to the above embodiments,
Various modifications can be made without changing the gist.

例えば電荷保持層及び導電層よりなる記録媒体の電荷保
持層に記録電極を密接させ、対電極を記録電極に隣接さ
せて静電記録を行う方式が提案されているが、本発明は
この方式に適用することができる。
For example, a method has been proposed in which electrostatic recording is performed by placing a recording electrode in close contact with the charge retaining layer of a recording medium consisting of a charge retaining layer and a conductive layer, and placing a counter electrode adjacent to the recording electrode. Can be applied.

又、対電極はその隣接する対電極の端部と対向している
記録電極との間で+2Eの電圧を生じたときに記録媒体
にゴーストを記録するおそれがある。
Further, when a voltage of +2E is generated between the end of the adjacent counter electrode and the opposing recording electrode, a ghost may be recorded on the recording medium.

そこで、対電極を同時に2つ以上選択して+2Eを加え
、これらと対向する複数の記録電極をその両側の1部分
づつを除いて選択して0とすることにより、その選択す
る複数の記録電極が対向する記録媒体の領域に対し対電
極の電圧を、実質的に均一にする方式が提案され、又対
電極を1つおきに選択する方式がある。
Therefore, by selecting two or more counter electrodes at the same time and adding +2E to them, and selecting a plurality of recording electrodes facing these counter electrodes except one part on each side and setting them to 0, the selected recording electrodes A method has been proposed in which the voltage of the counter electrode is made substantially uniform for the area of the recording medium where the counter electrodes are opposed, and another method is available in which every other counter electrode is selected.

本発明はこの両方式に適用することができる。The present invention can be applied to both types.

又、上記実施例において、直流電源の極性が逆であって
もよく、又上記静電記録方式以外の記録方式に本発明を
適用することができ、又、記録電極及び対電極を複数ラ
イン分設けてもよい。
Furthermore, in the above embodiment, the polarity of the DC power supply may be reversed, and the present invention can be applied to recording methods other than the electrostatic recording method described above, and the recording electrode and counter electrode may be arranged in multiple lines. It may be provided.

以上のように本発明による記録装置によれば記録用電極
及び対電極の一方の電極に非記録時よりも高い電圧を加
えるとともに他方に非記録時よりも低い電圧を加える駆
動回路を有し、記録用電源は同極性の一系統でありかつ
記録に充分な電圧よりも低いものが用いられるとともに
、駆動回路には前記一方の電極に加えられる電圧を微分
して前記電源電圧よりも高くする微分回路を有するため
、電源の簡単化及び低電圧化ならひに回路の簡単化を計
ることができ、記録電極相互間及び対電極相互間の耐電
圧を低くできる等の効果を奏する。
As described above, the recording device according to the present invention has a drive circuit that applies a higher voltage to one of the recording electrode and the counter electrode than when not recording, and applies a lower voltage to the other than when not recording, The recording power source is one system with the same polarity and lower voltage than sufficient for recording, and the drive circuit has a differentiator that differentiates the voltage applied to the one electrode to make it higher than the power supply voltage. Since it has a circuit, it is possible to simplify the power supply and lower the voltage, which in turn makes it possible to simplify the circuit, and has the effect of lowering the withstand voltage between the recording electrodes and between the counter electrodes.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図はそれぞれ従来の記録装置の一部を示
す回路図、第3図及び第4図はそれぞれ本発明の一実施
例の一部を示す回路図である。 211〜20m・・・記録電極、311〜31n・・・
対電極、321〜32m、33□〜33.・・・駆動回
路、TR3,TR4・・・駆動用トランジスタ、C2・
・・微分用コンデンサ、R1□・・・微分用抵抗。
1 and 2 are circuit diagrams each showing a part of a conventional recording apparatus, and FIGS. 3 and 4 are circuit diagrams each showing a part of an embodiment of the present invention. 211-20m...recording electrode, 311-31n...
Counter electrode, 321-32m, 33□-33. ...Drive circuit, TR3, TR4...Drive transistor, C2.
... Differential capacitor, R1□... Differential resistor.

Claims (1)

【特許請求の範囲】 1 群分けされ、かつ対応する位置のものが共通接続さ
れた複数の記録電極と複数の対電極とを用い、この記録
電極の電圧と対電極の電圧とを時分割で相加的に記録媒
体に作用させて記録を行う装置において、記録用電源と
、非記録時には前記記録媒体に対する作用電圧が記録に
不十分となるような電圧を前記記録電極及び対電極に加
え、記録時には前記記録媒体に対する作用電圧を記録に
十分な電圧とするために、前記記録電極および対電極の
一方の電極に非記録時よりも高い電圧を加えるとともに
他方に非記録時よりも低い電圧を加える駆動回路を有し
、 記録用電源は同極性の一系統でありかつ記録に充分な電
圧よりも低いものが用いられるとともに、駆動回路には
前記一方の電極に加えられる電圧を微分して前記電源電
圧よりも高くする微分回路を有することを特徴とする記
録装置。
[Claims] 1. Using a plurality of recording electrodes and a plurality of counter electrodes that are divided into groups and commonly connected at corresponding positions, the voltage of the recording electrode and the voltage of the counter electrode are time-divided. In an apparatus that performs recording by applying an additive action to a recording medium, applying a voltage to a recording power source and a voltage such that the voltage applied to the recording medium is insufficient for recording when not recording, to the recording electrode and the counter electrode, During recording, in order to make the voltage applied to the recording medium sufficient for recording, a voltage higher than that during non-recording is applied to one of the recording electrode and the counter electrode, and a lower voltage is applied to the other than during non-recording. The recording power source is one system with the same polarity and has a voltage lower than that sufficient for recording. A recording device characterized by having a differentiating circuit that makes the voltage higher than the power supply voltage.
JP50028844A 1975-03-10 1975-03-10 Kiroku house Expired JPS5833112B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50028844A JPS5833112B2 (en) 1975-03-10 1975-03-10 Kiroku house

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50028844A JPS5833112B2 (en) 1975-03-10 1975-03-10 Kiroku house

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP57031609A Division JPS57188387A (en) 1982-02-27 1982-02-27 Recorder

Publications (2)

Publication Number Publication Date
JPS51103733A JPS51103733A (en) 1976-09-13
JPS5833112B2 true JPS5833112B2 (en) 1983-07-18

Family

ID=12259665

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50028844A Expired JPS5833112B2 (en) 1975-03-10 1975-03-10 Kiroku house

Country Status (1)

Country Link
JP (1) JPS5833112B2 (en)

Also Published As

Publication number Publication date
JPS51103733A (en) 1976-09-13

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