JPS583379B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Field of Application of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device with improved wiring.

(2) Prior Art In integrated circuits, in so-called large-scale integrated circuits that have a large scale of integration, the number of interconnections between semiconductor elements constituting the circuits increases significantly.

As the number of wires increases in this way, the number of wires crossing each other also increases, causing various problems.

FIG. 1 explains one example of the above-mentioned problem, and shows a case where the wiring 1 intersects with a plurality of wirings.

It goes without saying that the lower the series resistance is, the more desirable the wiring conductor is. Therefore, the wiring should be made of aluminum (A
This is mainly done on metal conductors such as 1).

However, if the process of providing metal wiring is limited to one time, priority will be given to wiring such as power supply lines that require particularly low series resistance (here, 1), and other wiring that intersects with this wiring will be The parts 2a, 2a' and 2b, 2b' of the wiring which are not directly under the wiring 1 are made of metal conductors, and the parts directly under the wiring 1 are made of non-metallic conductors such as diffusion layers or polycrystalline silicon. I have no choice but to use 4b.

Connections between the nonmetallic conductors 4a and 4b and the metal conductors 2a to 2b' are made through interlayer communication holes 3a to 3b'.

At this time, the process of forming the nonmetallic conductors 4a and 4b is performed in the same process as the process of forming other parts on the semiconductor.

In this case, the sheet resistance of the diffusion layer etc. is extremely large, for example, 100 to 1000 times larger than that of aluminum, so a very large series resistance will be inserted in the wiring of the nonmetallic conductors 2a to 2b'. Even if 2a to 2b' are signal wires other than power supply lines, the delay time due to the wires becomes extremely large, which greatly affects the operating speed of the entire integrated circuit.

To avoid this problem, the wiring width of the non-metallic conductor 4a4b is usually set as shown in the figure.
b' is made larger to reduce the series resistance, but this increases the width W required for crossing, which causes another undesirable problem of increasing the number of integrated circuit chips.

Furthermore, the wiring capacitance increases due to the increase in the wiring area of the crossing portion, which causes damage such as generation of noise or delay in signal propagation, and the effect of reducing series resistance cannot be effectively utilized.

(3) Object of the Invention An object of the present invention is to provide a semiconductor device having wiring in which series resistance occurring at wiring intersections is reduced without increasing the area of an integrated circuit chip or the wiring capacity.

More specifically, it is an object of the present invention to provide a semiconductor device having wiring in which series resistance is reduced by effectively utilizing multiple layers of polycrystalline silicon without increasing the number of extra steps.

(4) Examples Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 2 shows an embodiment of the present invention.

1 is a wiring made of a metal body, 2a and 2a' are parts of the wiring to cross this wiring 1 made of a metal conductor, are made of the same metal conductor as the wiring 1, and the wiring 1 is formed. formed simultaneously in the process.

These wiring portions 2a, 2b' are interlayer communication holes 3a, 3a'
It is connected to the first layer polycrystalline silicon 5 and the second layer polycrystalline silicon 6 by.

FIG. 1B shows a cross-sectional structure taken along line AB in FIG. 1A.

In the figure, 7 is a silicon substrate, 8, 910 is a silicon oxide film for interlayer insulation, and the others are the same as those explained in FIG. 1.

The present invention is characterized by providing a plurality of layers of wiring members made of polycrystalline silicon at the intersections of the wirings and connecting them in parallel.

Further, in the semiconductor device of the present invention, there is no need to particularly increase the number of steps in order to provide a plurality of polycrystalline silicon layers.

In recent years, in I transistor/memory cell type memories using field effect transistors (hereinafter referred to as FETs), when forming the FETs, first and second layer gates made of polycrystalline silicon are used, and This gate 2
A layered method has been adopted, which is a well-known technique.

Descriptions of such memories can be found, for example, in C. Norman
Ahlquist et al.: A16384-Bit Dyna
mic RAM (IEEE Journal of So
lid-State Circuits, Vol, SC
-11, No. 5October 1976, p570
-573.

Therefore, when the present invention is applied to such a semiconductor device, when the first layer gate is formed of polycrystalline silicon, the polycrystalline silicon layer 5 shown in FIG. When forming the first interlayer insulating layer in FIG. 2B, the insulating layer 9 in FIG. 2B is also formed at the same time and from the same material.

Thereafter, when forming the second layer gate, the second polycrystalline silicon 6 shown in FIG. 2B is formed at the same time.

Thereafter, when forming a second interlayer insulating layer on the gate of this second layer, the second insulating layer 9 shown in FIG. 2B is formed simultaneously and from the same insulating material.

Thereafter, wirings 1, 2a, and 2a' are formed of Al in the same process.

According to the present invention, the effective series resistance of the crossover portion is approximately 1/2 that of the prior art.

Therefore, in order to obtain a predetermined series resistance, a wiring width that is half the wiring width required in the conventional technology is sufficient.Furthermore, since polycrystalline silicon 5 and 6 overlap, the wiring capacitance is also half that of the conventional technology. Become.

The manufacturing method of this embodiment may be completely the same as a normal manufacturing method, and there is no need to add any special manufacturing steps.

As described above, according to the present invention, the wiring resistance can be reduced to about half of the conventional one without increasing the integrated circuit chip and wiring capacitance, which was a problem with the conventional technology, and the performance of the integrated circuit can be greatly improved. can be improved.

The scope of application of the present invention is not limited to the scope of the above-mentioned embodiments. For example, the present invention can be applied as it is even if a larger number of layers of polycrystalline silicon are used, and aluminum ( It goes without saying that materials other than Al) such as tungsten (W) and molybdenum (Mo) can also be used.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating a conventional technique, and FIG. 2 is a diagram illustrating an embodiment of the present invention. 1, 2a, 2a', 2b, 2b'---- Metal conductor for wiring. 3a, 3a', 3b, 3b' ----- Interlayer communication hole, 4a, 4b... Nonmetallic conductor for wiring such as diffusion layer, 5, 6... Polycrystalline silicon ,7...
...Silicon substrate, 8,9,10...Silicon oxide film.

Claims (1)

[Scope of Claims] 1. In a semiconductor device having a first conductor for wiring and a second conductor for wiring provided to intersect with the first conductor, of the second conductor, A semiconductor device characterized in that a portion that intersects with the first conductor is formed by stacking a plurality of second conductor layers each having a conductivity lower than that of the first conductor. 2. The semiconductor device according to claim 1, wherein the second conductor layer is made of polycrystalline silicon.