JPS5840202B2 - switching regulator - Google Patents
switching regulatorInfo
- Publication number
- JPS5840202B2 JPS5840202B2 JP15621375A JP15621375A JPS5840202B2 JP S5840202 B2 JPS5840202 B2 JP S5840202B2 JP 15621375 A JP15621375 A JP 15621375A JP 15621375 A JP15621375 A JP 15621375A JP S5840202 B2 JPS5840202 B2 JP S5840202B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- circuit
- output
- amplifier
- switching regulator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- Control Of Voltage And Current In General (AREA)
- Dc-Dc Converters (AREA)
Description
【発明の詳細な説明】 本発明はスイッチングレギュレータに関する。[Detailed description of the invention] The present invention relates to switching regulators.
一般に、スイッチングレギュレータは、過電流出力及び
過電圧出力に対する保護機能を有し、電源装置に接続さ
れた負荷の保護及び電源装置自体の保護を行っている。Generally, a switching regulator has a protection function against overcurrent output and overvoltage output, and protects a load connected to the power supply device and the power supply device itself.
この様なスイッチングレギュレータの例としては、第1
図に示す様に、交流入力電圧を整流及び平滑回路を通し
て変換した直流電圧を、出力可変インバータによって再
度交流電圧に変換し、このインバータ出力を絶縁トラン
スにより昇圧(又は降圧)した後、整流及びp波回路を
通して直流出力電圧に変換する。An example of such a switching regulator is the first
As shown in the figure, the DC voltage obtained by converting the AC input voltage through a rectifying and smoothing circuit is converted back to AC voltage by the variable output inverter, and this inverter output is boosted (or stepped down) by an isolation transformer, then rectified and It is converted into a DC output voltage through a wave circuit.
可変インバータは、ドライブ回路を通してパルス幅変換
回路から供給されるパルス電圧に応じてON、OFF動
作を繰返す。The variable inverter repeats ON and OFF operations according to the pulse voltage supplied from the pulse width conversion circuit through the drive circuit.
パルス幅変換回路は、過電流検出増幅器から供給される
過電流信号電圧及び誤差電圧増幅器から供給される誤差
電圧に応シテハルス発生器から供給されるパルスのパル
ス幅を制御し、上記過電流信号電圧を基準電圧以下とす
る様に、又、直流出力電圧と基型圧との誤差が常に零に
なる様に、出力可変インバータのON。The pulse width conversion circuit controls the pulse width of the pulse supplied from the pulse generator in response to the overcurrent signal voltage supplied from the overcurrent detection amplifier and the error voltage supplied from the error voltage amplifier, and converts the overcurrent signal voltage to the overcurrent signal voltage supplied from the overcurrent detection amplifier. Turn on the variable output inverter so that it is below the reference voltage, and so that the error between the DC output voltage and base pressure is always zero.
OFFの動作時間比率を変化させる。Change the OFF operation time ratio.
誤差電圧増幅器はスイッチングレギュレータの直流出力
電圧を人力とし、又、過電流検出増幅器は通常整流及び
ろ波回路のOボルトラインに接続した抵抗器の電圧差を
入力とする。The error voltage amplifier uses the DC output voltage of the switching regulator as input, and the overcurrent detection amplifier uses the voltage difference between the resistors connected to the O volt line of the rectifier and filter circuit as input.
上述の様にしてスイッチングレギュレータの出力は安定
化され且つ過電流、過電圧から保護される。As described above, the output of the switching regulator is stabilized and protected from overcurrent and overvoltage.
従来、整流及びろ波回路RFを第2図に示す如く構成し
た場合、負荷LDが短絡すると平滑コンデンサC8が回
路から除かれた状態となる。Conventionally, when the rectifier and filter circuit RF is configured as shown in FIG. 2, when the load LD is short-circuited, the smoothing capacitor C8 is removed from the circuit.
即ち、チョークコイルLの充放電電流が大きくなり、過
電流検出抵抗R及びフライホイールダイオードDを通っ
て放電される電流■Lはリップル電圧を含んだ鋸歯状波
の大きなものとなる。That is, the charging/discharging current of the choke coil L increases, and the current L discharged through the overcurrent detection resistor R and the flywheel diode D becomes a large sawtooth wave including ripple voltage.
従って、過電流検出増幅器はリップル波形を含んだ脈動
電圧をパルス幅変換回路に供給することになる。Therefore, the overcurrent detection amplifier supplies a pulsating voltage including a ripple waveform to the pulse width conversion circuit.
−力、短絡された負荷にもチョークコイルLからリップ
ル電圧を含んだ大きな鋸歯状電流が流れ、これを人力す
る誤差電圧増幅器からパルス幅変換回路へ供給する誤差
電圧はリップル波形を持ったものとなる。- A large sawtooth current containing ripple voltage flows from the choke coil L to the short-circuited load, and the error voltage supplied from the error voltage amplifier to the pulse width conversion circuit has a ripple waveform. Become.
又、このような脈動電圧を除くべく誤差電圧増幅器内に
積分回路を挿入すると、その出力は位相遅れを生じたも
のとなる。Furthermore, if an integrating circuit is inserted into the error voltage amplifier in order to eliminate such pulsating voltage, the output thereof will have a phase lag.
上述のような過電流信号電圧及び誤差電圧LJ。Overcurrent signal voltage and error voltage LJ as described above.
パルス幅変換回路の動作を不安定にする要因となり、発
振や間欠動作等を生じ、電源装置から異音が発生したり
、さらには負荷に過大電流を流す等の異常現象を起す一
因となる。It can cause instability in the operation of the pulse width conversion circuit, causing oscillation and intermittent operation, causing abnormal noises from the power supply, and even causing abnormal phenomena such as excessive current flowing through the load. .
また、出力電流にリップルが大きく、かつコンデンサが
短絡状態で(Jスイッチングノイズの吸収も少なく、S
Nの悪化を生じ、出力電圧にノイズが加わ0、安定な電
源の構成が困難となる欠点があった。In addition, if the ripple in the output current is large and the capacitor is short-circuited (J switching noise absorption is low, S
This has the disadvantage that it causes deterioration of N, adds noise to the output voltage, and makes it difficult to construct a stable power supply.
本発明(j上記欠点を除去するためになされたもので、
過電流検出増幅器及び誤差電圧増幅器の出力の脈動成分
及びリップル戒分を積分回路で除去してパルス幅変換を
安定に行う様にしたスイッチングレギュレータを提供す
るものである。The present invention (j has been made to eliminate the above drawbacks,
The present invention provides a switching regulator that stably performs pulse width conversion by removing pulsating components and ripple components of the outputs of an overcurrent detection amplifier and an error voltage amplifier using an integrating circuit.
以下本発明の一実施例につき添付図面を参照して詳細に
説明する。Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.
尚、説明を簡単にするため従来のスイツチンレギュレー
タと同様の部分は説明を省略する。Incidentally, in order to simplify the explanation, the explanation of the parts similar to those of the conventional switch regulator will be omitted.
第3図に於て、10は誤差電圧増幅器を示し、この増幅
器10はスイッチングレギュレータの直流出力電圧を端
子Aに受け、この電圧を差動増幅器OA1に於て基準電
圧(図示の例ではツェナー電圧)と比較し、差電圧に応
じて+15Vから一15Vまで■オーダーで変化する出
力電圧を次段のパルス幅変換回路11に送る。In FIG. 3, reference numeral 10 denotes an error voltage amplifier. This amplifier 10 receives the DC output voltage of the switching regulator at terminal A, and transfers this voltage to the reference voltage (in the illustrated example, the Zener voltage) in the differential amplifier OA1. ), and the output voltage, which changes on the order of 2 from +15V to -15V according to the difference voltage, is sent to the next stage pulse width conversion circuit 11.
パルス幅変換回路11において誤差電圧増幅器10から
の出力電圧は抵抗R1、抵抗R2、およびコンデンサC
から成る積分回路により三角波に変換され、比較器CO
Mの一力の入力に与えられる。In the pulse width conversion circuit 11, the output voltage from the error voltage amplifier 10 is connected to a resistor R1, a resistor R2, and a capacitor C.
The comparator CO
It is given to the single force input of M.
−力、12は、過電流検出増幅器を示し、整流及びF波
回烙から過電流に伴う検出電圧を端子Bに受ける。Reference numeral 12 indicates an overcurrent detection amplifier, which receives at terminal B a detection voltage associated with an overcurrent from rectification and F-wave heating.
この検出電圧は、例えば0■〜−50mVの電圧に変換
された後、差動増幅器OA2の一力の入力に供給され、
基準電圧と比較される。This detection voltage is converted into a voltage of, for example, 0 to -50 mV, and then supplied to the single input of the differential amplifier OA2.
compared to a reference voltage.
この差動増幅器OA亨)らは入力電圧の差に応じて、例
えば+15Vから0■まで変化する出力電圧が発生され
、パルス幅変換回路11のコンデンサCと抵抗R2の間
に供給される。These differential amplifiers generate an output voltage that varies from, for example, +15V to 0V in accordance with the difference in input voltage, and is supplied between the capacitor C and the resistor R2 of the pulse width conversion circuit 11.
パルス幅変換回路11にはクロック信号が端子Pに供給
され、トランジスタTr1の導通を制御するとともにN
ANDゲートNAを制却する。A clock signal is supplied to the terminal P of the pulse width conversion circuit 11, which controls the conduction of the transistor Tr1 and also controls the conduction of the transistor Tr1.
Control AND gate NA.
比較器COMは積分回路からの三角波電圧を基準電圧と
比較して出力を発生しインバータを介してNANDゲー
トNAに入力される。The comparator COM compares the triangular wave voltage from the integrating circuit with a reference voltage to generate an output, which is input to the NAND gate NA via an inverter.
本発明は上記の様に構成したので、パルス幅変換回路1
1の積分回路に印加される電圧は、過電流検出増幅器1
2及び/又は誤差電圧増幅器10の出力電圧の大きさに
よって変化する。Since the present invention is configured as described above, the pulse width conversion circuit 1
The voltage applied to the integrating circuit 1 is the voltage applied to the overcurrent detection amplifier 1.
2 and/or the magnitude of the output voltage of the error voltage amplifier 10.
従って、比較器COMに供給される三角波の電圧の電圧
レベルガ増幅器10.12の出力電圧に比例して変化し
、これによってパルス幅変換回路11からのパルス幅が
変化し、出力可変インバータの出力のパルス幅を変化さ
せる。Therefore, the voltage level of the triangular wave voltage supplied to the comparator COM changes in proportion to the output voltage of the amplifier 10.12, thereby changing the pulse width from the pulse width conversion circuit 11 and changing the output of the variable output inverter. Vary the pulse width.
上述の動作を波形図を用いて説明する。The above operation will be explained using waveform diagrams.
第4図に示す如く、AはP端子に入力するクロック信号
、Bは比較器COMの入力電圧(三角波電圧)で、例え
ば、出力インバータの出力電圧が大きくなると、誤差電
圧増幅器10の出力は低くなり、コンデンサCへの充電
電流が増幅器10側へ流れるため、波形aの如く小さく
なる。As shown in FIG. 4, A is the clock signal input to the P terminal, and B is the input voltage (triangular wave voltage) of the comparator COM. For example, when the output voltage of the output inverter becomes large, the output of the error voltage amplifier 10 becomes low. Since the charging current to the capacitor C flows to the amplifier 10 side, the waveform becomes small as shown in waveform a.
−力、例えば、過電流検出増幅器12への過電圧が小さ
くなると、増幅器12の出力は大きくなり、波形すの如
く大きい三角波となる。- When the power, for example, the overvoltage applied to the overcurrent detection amplifier 12 becomes smaller, the output of the amplifier 12 becomes larger and becomes a large triangular wave as shown in the waveform.
即ち、増幅器10.12は入力電圧の内容によって三角
波は波形すからaに変化する。That is, the amplifiers 10 and 12 change the waveform from a triangular wave to a waveform depending on the content of the input voltage.
C1は比較器COMの入力端子が波形aのときのNAN
DゲートNAの入力信号を示し、又、C2は波形すのと
きのNANDゲートNAの入力信号を示す。C1 is NAN when the input terminal of comparator COM has waveform a.
The input signal of the D gate NA is shown, and C2 shows the input signal of the NAND gate NA when the waveform is 1.
これらの入力信号がクロックAと共にNANDゲートN
Aに入力すると、その出力は、波形aのときはDlの出
力となり、又、波形すのときはD2の出力となってドラ
イブ回路に供給される。These input signals together with clock A are connected to NAND gate N
When inputted to A, its output becomes the output of Dl when the waveform is a, and becomes the output of D2 when the waveform is a, and is supplied to the drive circuit.
即ち、誤差電圧増幅器10への直流出力電圧が増大する
とき、或は過電流検出増幅器12への検出電圧、従って
スイッチングレギュレータの負荷電流が増大するとき、
積分回路からの三角波電圧が小さくなり、比較器COM
の出力のパルス幅が減少することになる。That is, when the DC output voltage to the error voltage amplifier 10 increases, or when the detection voltage to the overcurrent detection amplifier 12 and therefore the load current of the switching regulator increases,
The triangular wave voltage from the integrator circuit becomes smaller and the comparator COM
The pulse width of the output will be reduced.
従って、スイッチングレギュレータの負荷に対する過電
流、過電圧の何れの場合も、パルス幅変換回路11内の
積分回路からの三角波電圧の波高値に交換し、これによ
ってドライブ回路に供給するパルス出力のパルス幅を決
めるものである。Therefore, in any case of overcurrent or overvoltage to the load of the switching regulator, the peak value of the triangular wave voltage from the integrating circuit in the pulse width conversion circuit 11 is exchanged, thereby changing the pulse width of the pulse output supplied to the drive circuit. It's up to you to decide.
誤差電圧増幅器10及び過電流検出増幅器12の出力に
脈動成分及びリップル戒分が含まれていても、積分回路
の抵抗R1,R2、及びコンデンサCを選択することで
平滑化され小さなものとなる。Even if the outputs of the error voltage amplifier 10 and the overcurrent detection amplifier 12 contain ripple components and ripple components, they are smoothed and reduced by selecting the resistors R1 and R2 of the integrating circuit and the capacitor C.
又、積分回路からの三角波電圧に脈動成分及びリップル
成分に帰因する変動分が残っていても、第4図から明ら
かな様に、NANDゲートNAの出力信号パルスは比較
器COMからの入力信号パルスの1/2になっており、
その変動分は1/2になったことに等しい。Furthermore, even if the triangular wave voltage from the integrating circuit contains fluctuations due to pulsation and ripple components, as is clear from FIG. 4, the output signal pulse of the NAND gate NA is equal to the input signal from the comparator COM It is 1/2 of the pulse,
The amount of change is equivalent to being reduced by 1/2.
叙上の様に、本発明のスイッチングレギュレータは、直
流出力電圧が変動すればその変動分を減少させる如く動
作し、換言すれば定電圧制御を行なうことができ、同様
に、負荷電流が変動すれば過電流に応じてパルス幅変換
回路の出力のパルス幅を変え、負荷電流の変動分が減少
する様に動作し、換言すれば定電流制御を行うことがで
きる。As described above, the switching regulator of the present invention operates to reduce the variation when the DC output voltage fluctuates, in other words, it can perform constant voltage control. For example, the pulse width of the output of the pulse width conversion circuit is changed in accordance with the overcurrent, and the circuit operates so as to reduce fluctuations in the load current. In other words, constant current control can be performed.
又、誤差電圧増幅器及び過電流検出増幅器の出力に脈動
成分及びリップル成分が含まれていてもパルス幅変換回
路は不安定な動作をしないから、従来の如くスイッチン
グレギュレータから異常音が発生したり、過大電流が流
れ或は過大電圧が発生することがなく、安定した動作が
得られる。Furthermore, even if the outputs of the error voltage amplifier and overcurrent detection amplifier contain pulsating components and ripple components, the pulse width conversion circuit does not operate unstablely, so abnormal noises may not be generated from the switching regulator as in the conventional case. Stable operation is achieved without excessive current flowing or excessive voltage occurring.
第1図は一般的なスイッチングレギュレータの一例を示
すブロック図、第2図は第1図の一部分を示す回路構成
図、第3図は本発明に係るスイッチングレギュレータの
一例を示す結線図、第4図は第3図の動作を示す波形図
である。
10・・・・・・誤差電圧増幅器、11・・・・・・パ
ルス幅変換回路、12・・・・・・過電流検出増幅器、
OAl、OA2・・・・・・差動増幅器、COM・・・
・・・比較器。FIG. 1 is a block diagram showing an example of a general switching regulator, FIG. 2 is a circuit configuration diagram showing a part of FIG. 1, FIG. 3 is a wiring diagram showing an example of a switching regulator according to the present invention, and FIG. The figure is a waveform diagram showing the operation of FIG. 3. 10...Error voltage amplifier, 11...Pulse width conversion circuit, 12...Overcurrent detection amplifier,
OAl, OA2...Differential amplifier, COM...
...Comparator.
Claims (1)
する手段と、該手段によって作られた交流電圧を直流電
圧に変換する回路と、該回路の出力電圧と基準電圧を比
較して誤差電圧を発生する誤差電圧増幅器と、前記回路
を流れる過電流を検出して過電流信号電圧を発生する過
電流検出増幅器と、前記誤差電圧及び過電流信号電圧に
応じてパルスを発生するパルス幅変換回路と、該パルス
を入力して前記変換手段を動作させるドライブ回路とを
備えるスイッチングレギュレータに於て、上記パルス幅
変換回路に積分は洛を設け、上記誤差電圧及び上記過電
流信号電圧を前記積分回路に供給し、該積分回路からの
出力電圧の波高値に応じて前記パルス変換回路から発生
するパルスのパルス幅を制御する如く構成したことを特
徴とするスイッチングレギュレータ。1. A means for converting DC voltage into AC voltage controlled by pulses, a circuit for converting the AC voltage produced by the means into DC voltage, and generating an error voltage by comparing the output voltage of the circuit with a reference voltage. an error voltage amplifier, an overcurrent detection amplifier that detects an overcurrent flowing through the circuit and generates an overcurrent signal voltage, and a pulse width conversion circuit that generates a pulse according to the error voltage and the overcurrent signal voltage; In the switching regulator, the switching regulator includes a drive circuit that operates the conversion means by inputting a pulse, and the pulse width conversion circuit is provided with an integral circuit, and the error voltage and the overcurrent signal voltage are supplied to the integration circuit. A switching regulator, characterized in that the switching regulator is configured to control the pulse width of the pulse generated from the pulse conversion circuit according to the peak value of the output voltage from the integration circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15621375A JPS5840202B2 (en) | 1975-12-29 | 1975-12-29 | switching regulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15621375A JPS5840202B2 (en) | 1975-12-29 | 1975-12-29 | switching regulator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5281545A JPS5281545A (en) | 1977-07-08 |
| JPS5840202B2 true JPS5840202B2 (en) | 1983-09-03 |
Family
ID=15622821
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15621375A Expired JPS5840202B2 (en) | 1975-12-29 | 1975-12-29 | switching regulator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5840202B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6412602U (en) * | 1987-07-14 | 1989-01-23 |
-
1975
- 1975-12-29 JP JP15621375A patent/JPS5840202B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6412602U (en) * | 1987-07-14 | 1989-01-23 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5281545A (en) | 1977-07-08 |
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