JPS5843196A - Controlling method for motor - Google Patents

Abstract

PURPOSE:To accurately control a motor by recording a data period signal so that the duty ratio is ''1'' and a pulse which has maximum period of recording signals is included, and reproducing it, thereby obtaining a data synchronization signal. CONSTITUTION:A data synchronization signal is recorded on a disc 1 so that the duty ratio is ''1'' and the pulse in which the period is maximum in the recording signals is included, is reproduced by a pickup, the signal having ''1'' of duty ratio is detected by a detector 3, the signal having maximum period is detected by the maximum period detector 4, and is applied to an AND gate 13, thereby obtaining a data synchronization signal. Then, it is compared by phase comparator 6 with a reference signal from a crystal oscillator 5, therby controlling the rotation of the motor 8. Accordingly, the motor 8 can be stably and accurately controlled, thereby rotating the disc 1 at the constant linear speed and enabling to demodulate an accurate data.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides, for example, a PCM (pulse code modification 11) signal i
This invention relates to a motor control method that can be applied to a motor for rotating a PCM disk on which TS records are recorded.

Recently, a digital audio disc has been proposed in which an audio signal (analog signal) is converted into a PCI signal (digital signal), optically recorded on a disc, and reproduced. In this case, it has been considered to record the digital data onto the disk using an appropriate digital modulation method, such as 8/14 conversion 11 (converting 8-bit data to 14-bit data - called rMRII). There is. In addition, since recording and playback of conventional discs is performed while keeping the rotational speed constant, the upper limit of linear recording density is limited by the linear recording density at the innermost circumference, but there is a margin of several times greater at the outermost circumference. I had to keep it, and wasted it.

For this reason, in order to keep the linear velocity constant, the rotational speed is varied between the outer and inner peripheries, and by keeping the linear velocity constant, the recording time is extended or the disk is made smaller.

In order to keep the linear velocity constant, the rotational speed must be constantly and continuously changed as one moves from the outer circumference to the inner circumference or from the inner circumference to the outer circumference.

Various types of PCI signal formats can be considered, but generally there is one that consists of an IT data synchronization signal and data.As shown in Figure 1, the frame consists of data synchronization bits and The data synchronization signal is a comparison signal for a motor control circuit to continuously change the rotational speed of a disk whose linear velocity is constant, and a data synchronization signal for specifying the starting point of the data portion. By the way, when playing a signal recorded using a digital modulation method on a disk with a constant linear velocity, digital demodulation is performed using a phase-locked loop (Pi, L), etc. The signal (data synchronization signal, data) cannot be demodulated unless the motor reaches a predetermined rotation speed.Therefore, it is extremely difficult to control the rotational speed of the motor with high precision using the data synchronization signal.

Therefore, in the present invention, a data synchronization signal is recorded on a disk so as to include a pulse with a density ratio of 11 m and a period that is the maximum among the recorded signals, and the reproduced signal reproduced from this disk is From inside, duty ratio 1
11 and the signal with the maximum period is used as a synchronization signal, and the motor rotation is controlled based on this reproduction synchronization signal to rotate the disk at a constant linear velocity, enabling accurate data demodulation with J2t. That is.

Hereinafter, it will be explained in detail based on Examples. In this embodiment, one frame consists of s88 channel bits, of which 24 channel bits are allocated to data synchronization signals.

The data synchronization signal includes one cycle of 11 channel bit pulses (duty ring @1'') (see Figure 1).In addition, the period of this pulse is the maximum in the recording signal (Digital data is As mentioned above, it is recorded in <MWM114 modulation. By 17M modulation, 8 data bits of data are rekeyed to 14 channel bits of data, but the number of data that can be expressed with 18 bits is 14.
Since the number of data that can be expressed by bits is naturally large, some restrictions can be placed on 14 channel bit data.For example, if 14 channel bit data is recorded using the NRZI method, the signal will be inverted. It is possible to impose a restriction that the interval is 3 channel ss bits or more and 11 channel bits or less. In 117M modulation, signal inversion intervals of 11 channel bits do not occur consecutively. However, in the data, the duty ratio of channel bits smaller than 11 channel bits is 111fJp.
4 pulses (for example, pulses with a duty ratio of 11" for 6 channel bits shown in Fig. 1) are included. Therefore, by using the pickup from the disk on which the data synchronization signal and data are recorded using the method described above, By reproducing the signal and detecting the one with the duty ratio @11 and the maximum period among the reproduced signals, it is possible to extract the data synchronization signal without digital demodulation.The present invention solves this point. The focus is on

Hereinafter, a detailed explanation will be given with reference to FIG. 2 showing a block diagram of an apparatus for implementing the method according to the present invention, and FIG. 3 showing an operational waveform diagram thereof. The signals recorded on the disk (1) are picked up by a pickup (2) (□ a device that converts recorded signals into electrical signals optically, electromechanically, or electrostatically depending on the recording format on the disk). (Part 3)
See Figure a]. This reproduced signal (a) has a duty ratio @1
m detection circuit (33), and only a signal with a duty ratio of 11'' is detected from the reproduced signal (&) (see Figure 3). - Expo raw signal (aJ is applied to the maximum period detection circuit (4)
), and the signal 1G) having the maximum period (maximum signal inversion interval) is detected from the reproduced signal 1m) (see FIG. 30).

This maximum period detection signal (0) and the aforementioned duty ratio 1
1'' detection signal 1b) is applied to the AND gate (to), the output 4 of the AND gate I becomes a data synchronization signal (see FIG. 30).

This data synchronization signal (0) is compared with the reference signal from the crystal oscillator (5:) by the i-phase comparator (6), and the error output is applied to the motor (8) via the low-pass filter (7). One step is to stably control the rotation of the motor (8). In other words, the pickup (2) and the duty ratio "
11 detection circuit ■, maximum R' continuous detection dml path (41, AND gate (to), crystal oscillation sts+J-phase comparator (6),
Low, ・111 ・:1 It constitutes a pass filter (7) and a motor (s+sj phase-locked loop (PLL) (9), and the rotation of the monitor (8) is controlled stably and accurately. It is.

After the rotation of the motor is accurately controlled in this manner, accurate demodulation of digital data becomes possible. That is, the reproduced signal bullet) is input to the KPM demodulation circuit αG and demodulated, and then applied to the digital processing circuit ALL where processing such as data synchronization control and error correction is performed.
- It is input to the A converter (2) and converted into an audio signal.

Since such a configuration is outside the gist of the present invention, detailed explanation will be omitted.

In addition, after the disk reaches a predetermined rotational speed and a constant linear velocity is achieved, and it becomes possible to digitally detect the data synchronization signal, the motor is controlled using the digitally detected synchronization signal C. It is more convenient. This is because if the playback data synchronization signal is lost due to dropouts, etc., this loss cannot be compensated for using a method that uses duty ratio detection output, but a digital detection method that uses PILL, for example, cannot compensate for this loss. , if the reproduced data synchronization signal is missing, a compensation data synchronization signal can be generated to compensate for this, and by using this, stable and accurate monitor control becomes possible.

Next, a specific example of the duty ratio "1" detection circuit (J) will be explained with reference to FIG. The interval is measured and compared, and if the difference between the two is within a predetermined tolerance value, a duty ratio of 1 m detection output is output. When the duty ratio is ``1・
It is considered as 1. The reason for this configuration is that the reproduced signal does not have a perfect duty ratio of 1'' due to waveform distortion, noise, etc.

The reproduced signal +at is input to the binary counter via two inverters CIIC (11) and is also input to the binary counter (to) via one inverter (to). Counter l!9 (to) is in the reset state when the L level signal is applied to the reset terminal, and counts the clock pulses output from the crystal oscillator (to) when the level signal is applied.Therefore, the counter (to) is in the reset state. )
The H level signal reversal interval is also very low.
The L-level signal inversion interval is measured at each step. The purpose of the inverter (Ic(l)) is to delay the signal, and the reason for this is as follows.That is, when the signal is inverted from H level to L level, the H level output of the inverter (to) causes The contents of the counter (2) at that point are the latch circuit (
), but the inverter (!InC
If this delay is not performed by III, the counter (to) will be reset first, and there is a possibility that the latch operation will not be possible. Therefore, by inserting the inverter (31(2)),
□This is to ensure that the latch operation is performed first.As a result, the constant value of the inversion interval of the H level signal becomes smaller by the value equivalent to the delay of one inverter,
This value is extremely small, and the measured value of the inversion interval of the L level signal is also reduced by a value corresponding to the delay caused by the inverter, so there is no problem in practice.

In this manner, the signal inversion intervals between adjacent H and L levels are measured by counters, respectively, and the measured trace values are latched in the latch circuit ci. Then, both latch outputs are applied to a subtraction circuit (TO), and a comparison circuit (TO) detects whether or not the difference is within a predetermined tolerance value. That is, the clock pulse output from the crystal oscillator (to) is divided into 1/11 by a branch circuit, and then measured by a two-way counter.
The measured value is latched by a latch circuit. When the output of the subtraction circuit (to) is smaller than this latch output, the detection output with a duty ratio of 11" (field comparison circuit (to))
Get more.

In addition, in this example, measurement should be carried out only! 1H level and L
The difference between the level signal inversion intervals is 1711 of the inversion interval.
The signal inversion intervals of the following and red 1 levels are assumed to be equal, and a detection output with a duty ratio of 1 is obtained. There are 7 bits for 11 channels, so there are only 1
This is because it is necessary to distinguish between 1 channel bit and 10 channel bit.Furthermore, the higher the frequency of the clock pulse, the more accurate the measurement of the signal inversion interval.・、
Next, a specific example of the maximum cycle detection time, 1i (Q, will be explained with reference to the block diagram of FIG. 4. In this embodiment, a part of the circuit width) is the duty ratio @
1” detection circuit (shared with J).

In other words, the circuit for measuring the period (signal inversion interval) is shared, and the maximum period detection signal is configured to receive the measured value of the signal inversion interval, that is, the latch output of the latch circuit. .

Now, the latch circuit measures the maximum period (maximum signal inversion interval) of the reproduced signal (aJ) within a certain period of time, that is, the period of the divided output obtained by dividing the oscillation output of the oscillator (to) with the 1/N frequency divider. The comparator compares the value that was previously latched in the latch circuit (the slope and the value of the latch circuit at that point) and finds that the value (ml) is larger. In addition, when this measured value (phrase is the measured value of the signal inversion interval of a pulse with a duty ratio of 1 m), the AND gate (- output is 5 levels, so at the R level output of B, the latch at that point is 4. Therefore, the 17H frequency divider (
The contents of the latch circuit immediately before it is cleared to 8 at the output of ``1'' is 1... within a certain period of time! This is the measured value of the maximum signal reversal interval. Therefore, the contents of the latch circuit are transferred to the latch circuit at regular intervals using the output of the 17M frequency divider, and the contents of the latch circuit are cleared. Then, the maximum value latched in the latch circuit within a certain period of time and the value measured at the present moment (latched contents of the latch circuit) are subtracted using a subtracter, and this value is determined as a predetermined allowable value. Whether or not it is within the value is detected using the comparison a@ in the same manner as in the case of duty ratio @11 detection.

Then, if it is within the predetermined tolerance, this live comparator -
(03 is the maximum period detection signal.As is clear from the previous explanation, even when a signal with a signal inversion interval of 11 channel bits included in the data is reproduced, the maximum period detection signal (q ) occurs.Therefore, this signal (
The AND output of 03 and the aforementioned duty ratio "1" detection signal (bJ becomes a true data synchronization signal (dj).

Furthermore, the reason for the configuration in which the constant value of the maximum signal inversion interval is cleared at regular intervals is that until a constant linear velocity is achieved,
This is because the running of the recording medium (disc) is unstable, and the measured value of the maximum signal inversion interval is not constant. The certain period is set to be longer than the time required to reproduce at least one frame of the signal (even if the speed is less than a predetermined speed).

According to the present invention described above, the data synchronization signal is recorded so as to include a pulse having a duty ratio of 11 and a large period in the recording signal, and from the reproduced signal, a signal with a duty ratio of @11 is recorded. Moreover, since the signal with the maximum period is detected as a data synchronization signal and this is used to control the motor for running the recording medium, the motor can be controlled stably and correctly. is possible. As a result, accurate demodulation of digital data can be expected.

In other words, since the duty ratio and the signal inversion interval (period) are utilized, the data synchronization signal can be detected even if the rotation speed of the recording medium deviates from a predetermined number.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the frame configuration, Fig. 2 is a block diagram of a device for realizing the motor control method according to the present invention, Fig. 3 is its operating waveform diagram, and Fig. 4 is a duty ratio @ 1'' detection. It is a block diagram showing a specific example of a circuit and a maximum cycle detection circuit. (3)... Duty ratio @1m detection circuit, +4) -
- Maximum period detection circuit, (9)...phase locked loop.

Claims (1)

[Claims] The digital data is recorded by a predetermined digital transformation Il, and the synchronization signal added to the digital data includes a pulse whose duty ratio is Il+1# and whose period is the maximum among the recorded signals. A method of controlling a motor for driving a recording medium recorded on the recording medium during reproduction, wherein the signal having a duty ratio of 11'' and a maximum cycle is selected from reproduction signals reproduced from the recording medium. A rumor control method characterized in that the rotation of a motor for running the recording medium is controlled based on the synchronization signal by detecting the synchronization signal. (2) Maximum When detecting a periodic signal, the signal reversal interval of the maximum periodic signal is measured and latched at every fixed period, and the difference between this latch content and the measured value of the signal reversal interval of the current signal is within a predetermined tolerance value. The motor control method according to claim 1, characterized in that the detection signal of the maximum period signal is obtained when: (3) When detecting the duty ratio of the reproduced signal: adjacent high level signals and low level signals The signal section is measured using clock pulses, and when the difference between the two is within a predetermined tolerance value, the duty ratio is ``1'' (detection signal bar).The detected synchronization signal is input to the phase comparator that makes up the phase-locked loop. 1. The control method according to claim 1, 2 or 3, wherein the rotation of the motor is controlled by a phase locked loop of a Ja-5 lever.