JPS5843550A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS5843550A
JPS5843550A JP56141101A JP14110181A JPS5843550A JP S5843550 A JPS5843550 A JP S5843550A JP 56141101 A JP56141101 A JP 56141101A JP 14110181 A JP14110181 A JP 14110181A JP S5843550 A JPS5843550 A JP S5843550A
Authority
JP
Japan
Prior art keywords
lead
metal plate
hole
solder
plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56141101A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6344302B2 (de
Inventor
Hirotoshi Toida
裕俊 戸井田
Toshiaki Hagiwara
利明 萩原
Yasuhiro Masuko
益子　康弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Industry and Control Solutions Co Ltd
Original Assignee
Hitachi Engineering Co Ltd Ibaraki
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Engineering Co Ltd Ibaraki, Hitachi Ltd filed Critical Hitachi Engineering Co Ltd Ibaraki
Priority to JP56141101A priority Critical patent/JPS5843550A/ja
Publication of JPS5843550A publication Critical patent/JPS5843550A/ja
Publication of JPS6344302B2 publication Critical patent/JPS6344302B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/02—Manufacture or treatment of conductive package substrates serving as an interconnection, e.g. of metal plates
    • H10W70/023—Connecting or disconnecting interconnections thereto or therefrom, e.g. connecting bond wires or bumps

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP56141101A 1981-09-09 1981-09-09 半導体装置 Granted JPS5843550A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56141101A JPS5843550A (ja) 1981-09-09 1981-09-09 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56141101A JPS5843550A (ja) 1981-09-09 1981-09-09 半導体装置

Publications (2)

Publication Number Publication Date
JPS5843550A true JPS5843550A (ja) 1983-03-14
JPS6344302B2 JPS6344302B2 (de) 1988-09-05

Family

ID=15284206

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56141101A Granted JPS5843550A (ja) 1981-09-09 1981-09-09 半導体装置

Country Status (1)

Country Link
JP (1) JPS5843550A (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63280122A (ja) * 1987-05-13 1988-11-17 Yoshida Tekkosho:Kk コンクリ−ト，モルタル面補修工法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63280122A (ja) * 1987-05-13 1988-11-17 Yoshida Tekkosho:Kk コンクリ−ト，モルタル面補修工法

Also Published As

Publication number Publication date
JPS6344302B2 (de) 1988-09-05

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