JPS5847713Y2 - Thin film hybrid circuit for thermal recording head - Google Patents

Thin film hybrid circuit for thermal recording head

Info

Publication number
JPS5847713Y2
JPS5847713Y2 JP6333182U JP6333182U JPS5847713Y2 JP S5847713 Y2 JPS5847713 Y2 JP S5847713Y2 JP 6333182 U JP6333182 U JP 6333182U JP 6333182 U JP6333182 U JP 6333182U JP S5847713 Y2 JPS5847713 Y2 JP S5847713Y2
Authority
JP
Japan
Prior art keywords
thin film
glass layer
hybrid circuit
thermal recording
recording head
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP6333182U
Other languages
Japanese (ja)
Other versions
JPS57203564U (en
Inventor
正行 浅香
光彦 田代
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP6333182U priority Critical patent/JPS5847713Y2/en
Publication of JPS57203564U publication Critical patent/JPS57203564U/ja
Application granted granted Critical
Publication of JPS5847713Y2 publication Critical patent/JPS5847713Y2/en
Expired legal-status Critical Current

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Description

【考案の詳細な説明】 この考案は発熱素子としての薄膜抵抗体および他の能動
あるいは受動素子を同一基板上で薄膜配線導体にて配線
した感熱記録ヘッド用薄膜混成回路に関する。
[Detailed Description of the Invention] This invention relates to a thin film hybrid circuit for a thermal recording head in which a thin film resistor as a heating element and other active or passive elements are wired on the same substrate using thin film wiring conductors.

一般に、感熱記録用ヘッドのような薄膜抵抗体を有する
薄膜混成回路においては、薄膜抵抗体部分の抵抗値の均
一性、再現性等の点から、基板としてガラス層で被覆さ
れたセラミック基板が用いられる。
Generally, in a thin film hybrid circuit having a thin film resistor such as a thermal recording head, a ceramic substrate covered with a glass layer is used as the substrate from the viewpoint of uniformity and reproducibility of the resistance value of the thin film resistor part. It will be done.

第1図は従来の薄膜混成回路の断面図であり、セラミッ
ク基板1上にガラス層2を形威し、その上に真空蒸着法
、メッキ法等により薄膜抵抗層および薄膜金属層を被着
し化学蝕刻法等により薄膜抵抗体3および薄膜配線導体
4を形成する。
FIG. 1 is a cross-sectional view of a conventional thin film hybrid circuit, in which a glass layer 2 is formed on a ceramic substrate 1, and a thin film resistance layer and a thin film metal layer are deposited thereon by vacuum evaporation, plating, etc. A thin film resistor 3 and a thin film wiring conductor 4 are formed by chemical etching or the like.

そして、薄膜抵抗体3の周辺部においてダイオード、ト
ランジスタ等の半導体能動素子やチップコンテ゛ンサ、
チップ抵抗等の受動素子5を、半田付け、熱圧着、超音
波ボンディング等の方法で薄膜配線導体4上に接続して
いる。
In the peripheral area of the thin film resistor 3, semiconductor active elements such as diodes and transistors, chip capacitors, etc.
A passive element 5 such as a chip resistor is connected onto the thin film wiring conductor 4 by a method such as soldering, thermocompression bonding, or ultrasonic bonding.

ところが、このように形成される薄膜混成回路では、上
記素子5の取付は時における熱、機械的圧力によりガラ
ス層2が破壊することがあり、その結果これら素子5の
接続部の薄膜配線導体4′の剥離、断線さらには半導体
能動素子の破壊を招くおそれがある。
However, in the thin film hybrid circuit formed in this way, the glass layer 2 may break due to heat and mechanical pressure during the mounting of the elements 5, and as a result, the thin film wiring conductor 4 at the connection part of these elements 5 may break. There is a risk of peeling off the wire, disconnection, and even destruction of the semiconductor active element.

この考案は上記問題点に鑑みなされたもので、その目的
は半導体能動素子等の薄膜抵抗体以外の素子部品の取付
は時におけるセラミック基板上のガラス層の破壊を防ぎ
、もって薄膜配線導体の剥離や断線、素子の破壊を防ぐ
と共に、感熱記録ヘッドとして有用な構造とした感熱記
録ヘッド用薄膜混成回路を提供するにある。
This idea was devised in view of the above problems, and its purpose is to prevent the glass layer on the ceramic substrate from breaking when mounting element parts other than thin film resistors such as semiconductor active elements, thereby preventing peeling of the thin film wiring conductor. It is an object of the present invention to provide a thin film hybrid circuit for a thermal recording head, which prevents wire breakage and element destruction, and has a structure useful as a thermal recording head.

この考案は、発熱素子としての薄膜抵抗体およびその接
続部の薄膜配線導体とセミツク基板との間にはガラス層
を介在させるが、薄膜配線導体のうち薄膜抵抗体以外の
能動あるいは受動素子の接続部の導体はガラス層を介さ
ずに直接セラミック基板上に形成することにより、これ
らの素子の取付は時に上記ガラス層に熱や圧力が加わら
ないようにしたものである。
In this idea, a glass layer is interposed between the thin film resistor as a heating element, the thin film wiring conductor at the connection part thereof, and the semiconductor substrate, but active or passive elements other than the thin film resistor are connected to the thin film wiring conductor. By forming the conductors directly on the ceramic substrate without using a glass layer, these elements can be mounted without applying heat or pressure to the glass layer.

このようなすることで、ガラス層の破壊を防止すること
ができる。
By doing this, destruction of the glass layer can be prevented.

また、このガラス層は本来、前述した如く薄膜抵抗体の
抵抗値の均一性、再現性を得るためのものであるから、
上記のように薄膜抵抗体以外の接続部における薄膜配線
導体下部のガラス層を除去することに何ら問題はない。
In addition, since this glass layer is originally intended to obtain uniformity and reproducibility of the resistance value of the thin film resistor as mentioned above,
As mentioned above, there is no problem in removing the glass layer below the thin film wiring conductor at the connection portion other than the thin film resistor.

またこの考案においては、セラミック基板のガラス層で
被覆された領域を凸部としてここに薄膜抵抗体を形成す
る。
Further, in this invention, a thin film resistor is formed in a region covered with a glass layer of a ceramic substrate as a convex portion.

従って薄膜抵抗体を発熱抵抗体として用いる感熱記録ヘ
ッドを構成した場合に、ヘッドに摺接して走行する感熱
記録紙をそれ程わん曲させなくても、これに対して発熱
抵抗体の部分のみを良好な接触圧で対向されることがで
きる。
Therefore, when configuring a thermal recording head that uses a thin film resistor as a heating resistor, the thermal recording paper that runs in sliding contact with the head does not have to be bent that much, but only the heating resistor part can be easily bent. can be opposed with a certain contact pressure.

以下第2図を参照してこの考案の一実施例を説明する。An embodiment of this invention will be described below with reference to FIG.

第2図はこの考案に係る薄膜混成回路の断面図を示した
ものである。
FIG. 2 shows a cross-sectional view of the thin film hybrid circuit according to this invention.

すなわち、セラミック基板1にはガラス層2が被覆され
て凸部を形威しており、薄膜抵抗体3およびその接続部
の薄膜配線導体4はこのガラス層2上に形成されている
が、薄膜配線導体のうちダイオード、1−ランジスタ等
の半導体能動素子あるいはチップコンテ゛ンサ、チップ
抵抗等の受動素子(以下単に素子という)5の接続部の
導体4′は、セラミック基板1上に直接形成されている
That is, the ceramic substrate 1 is covered with a glass layer 2 to form a convex portion, and the thin film resistor 3 and the thin film wiring conductor 4 at the connection portion thereof are formed on this glass layer 2. Among the wiring conductors, the conductor 4' at the connection part of the semiconductor active element such as a diode or transistor or the passive element (hereinafter simply referred to as an element) 5 such as a chip capacitor or chip resistor is formed directly on the ceramic substrate 1. .

このような薄膜混成回路を形成するには、まずセラミッ
ク基板1上の上記素子5の配線領域以外の部分にのみガ
ラス層2を最初から形成するか、あるいは基板1上に全
面にガラス層2を形成した後上記配線領域のみ化学蝕刻
法等によりガラス層を除去して基板1を露出させる。
To form such a thin film hybrid circuit, first, the glass layer 2 is formed only on the ceramic substrate 1 except for the wiring area of the element 5, or the glass layer 2 is formed on the entire surface of the substrate 1. After the formation, the glass layer is removed only in the wiring area by chemical etching or the like to expose the substrate 1.

次に真空蒸着法、メッキ法等により薄膜抵抗層および薄
膜金属層を形威し、この各薄膜層を化学蝕刻法等により
薄膜抵抗体3および薄膜配線導体4とする。
Next, a thin film resistance layer and a thin film metal layer are formed by a vacuum deposition method, a plating method, etc., and each thin film layer is formed into a thin film resistor 3 and a thin film wiring conductor 4 by a chemical etching method or the like.

そしてセラミック基板1が露出している前記配線領域の
薄膜配線導体4′上に、素子5を半田付け、熱圧着、超
音波ポンチ゛イング等の方法で接続する。
Then, the element 5 is connected to the thin film wiring conductor 4' in the wiring area where the ceramic substrate 1 is exposed by a method such as soldering, thermocompression bonding, or ultrasonic punching.

このように形成された薄膜混成回路においては、素子5
がセラミック基板1の露出部分に形成された薄膜配線導
体4′上に接続されるため、素子5の取付時における熱
や圧力によって、ガラス層2が破壊することがない。
In the thin film hybrid circuit formed in this way, the element 5
Since the glass layer 2 is connected to the thin film wiring conductor 4' formed on the exposed portion of the ceramic substrate 1, the glass layer 2 will not be destroyed by heat or pressure when the element 5 is attached.

従って、ガラス層2の破壊に起因する素子5の接続部の
薄膜配線導体4′の剥離、断線、半導体素子の破壊等の
ない薄膜混成回路が容易に再現性良く得られる。
Therefore, a thin film hybrid circuit can be easily obtained with good reproducibility without peeling of the thin film wiring conductor 4' at the connecting portion of the element 5, disconnection, or destruction of the semiconductor element due to the destruction of the glass layer 2.

また、引張り強度の点でもガラスの150kg/cm2
に対し、セラミックは1500 kg/cm2と約10
倍の差があるので、この発明の如くセラミック基板上に
直接薄膜抵抗体以外の能動素子および受動素子を取付け
た方が機械的に安定であるという利点も有する。
Also, in terms of tensile strength, glass has a tensile strength of 150kg/cm2.
On the other hand, ceramic has a weight of 1500 kg/cm2, which is about 10
Since there is a double difference, mounting active elements and passive elements other than the thin film resistor directly on the ceramic substrate as in the present invention also has the advantage of being more mechanically stable.

また、薄膜抵抗体3を発熱抵抗体として用いる感熱記録
ヘッドを構成した場合には、記録紙とヘッドの無用な摩
擦を防止して信頼性の高い感熱記録を行うことが可能と
なる。
Further, when a thermal recording head is configured using the thin film resistor 3 as a heating resistor, it is possible to prevent unnecessary friction between the recording paper and the head and perform highly reliable thermal recording.

なお、この考案は図示したような単層配線のみならず、
多層配線構造の薄膜混成回路にも適用し得る。
Note that this idea is not limited to single-layer wiring as shown in the diagram.
It can also be applied to thin film hybrid circuits with multilayer wiring structures.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の薄膜混成回路の断面図、第2図はこの考
案の一実施例を示す薄膜混成回路の断面図である。 1・・・・・・セラミック基板、2・・・・・・ガラス
層、3・・・・・・薄膜抵抗体、4,4′・・・・・・
薄膜配線導体、5・・・・・・薄膜抵抗体以外の能動あ
るいは受動素子。
FIG. 1 is a sectional view of a conventional thin film hybrid circuit, and FIG. 2 is a sectional view of a thin film hybrid circuit showing an embodiment of this invention. 1... Ceramic substrate, 2... Glass layer, 3... Thin film resistor, 4, 4'...
Thin film wiring conductor, 5... Active or passive element other than thin film resistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] セラミック基板上に薄膜配線導体および発熱素子として
の薄膜抵抗体と共に他の能動あるいは受動素子を集積し
てなる感熱記録ヘッド用薄膜混成回路において、前記セ
ラミック基板にガラス層で被覆された凸部とガラス層の
ない領域とを設け、前記薄膜抵抗体および薄膜配線導体
を前記ガラス層で被覆された凸部に形成し、前記薄膜配
線導体の一部を前記ガラス層のない領域に延在させてこ
の延在部を前記薄膜抵抗体以外の能動あるいは受動素子
の端子との接続部としたことを特徴とする感熱記録ヘッ
ド用薄膜混成回路。
In a thin film hybrid circuit for a thermal recording head in which a thin film wiring conductor, a thin film resistor as a heat generating element, and other active or passive elements are integrated on a ceramic substrate, a convex portion covered with a glass layer and a glass layer are provided on the ceramic substrate. the thin film resistor and the thin film wiring conductor are formed on the convex portion covered with the glass layer, and a part of the thin film wiring conductor is extended to the region without the glass layer. A thin film hybrid circuit for a thermal recording head, characterized in that the extended portion is a connection portion to a terminal of an active or passive element other than the thin film resistor.
JP6333182U 1982-04-30 1982-04-30 Thin film hybrid circuit for thermal recording head Expired JPS5847713Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6333182U JPS5847713Y2 (en) 1982-04-30 1982-04-30 Thin film hybrid circuit for thermal recording head

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6333182U JPS5847713Y2 (en) 1982-04-30 1982-04-30 Thin film hybrid circuit for thermal recording head

Publications (2)

Publication Number Publication Date
JPS57203564U JPS57203564U (en) 1982-12-24
JPS5847713Y2 true JPS5847713Y2 (en) 1983-10-31

Family

ID=29859456

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6333182U Expired JPS5847713Y2 (en) 1982-04-30 1982-04-30 Thin film hybrid circuit for thermal recording head

Country Status (1)

Country Link
JP (1) JPS5847713Y2 (en)

Also Published As

Publication number Publication date
JPS57203564U (en) 1982-12-24

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