JPS5848100U - Sampling hold circuit - Google Patents
Sampling hold circuitInfo
- Publication number
- JPS5848100U JPS5848100U JP13987281U JP13987281U JPS5848100U JP S5848100 U JPS5848100 U JP S5848100U JP 13987281 U JP13987281 U JP 13987281U JP 13987281 U JP13987281 U JP 13987281U JP S5848100 U JPS5848100 U JP S5848100U
- Authority
- JP
- Japan
- Prior art keywords
- sampling
- circuit
- holding
- holding circuit
- hold circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Analogue/Digital Conversion (AREA)
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のサンプリングホールド回路のブロック図
、第２図はスイッチとしてＦＥＴを使用したサンプリン
グホールド回路のブロック図、第３−図はスパイクノイ
ズの波形図、第４図はこの考案のサンプリングホールド
回路のブロック図、第５図はサンプリングパルスと、ス
パイクノイズの波形図を示す。
図中、１は被サンプル信号源、２は入力バッファ回路、
３はスイッチ、４はコンデンサ、５は出力バッファ回路
、１１は並列時定数回路、１２はスイッチ、１３はコン
デンサ、１４はバッファ回路、１５は反転増幅器、１６
はカップリングコンデンサを示す。 ′Figure 1 is a block diagram of a conventional sampling and holding circuit, Figure 2 is a block diagram of a sampling and holding circuit using FET as a switch, Figure 3 is a waveform diagram of spike noise, and Figure 4 is a sampling and holding circuit of this invention. The block diagram of the circuit, FIG. 5, shows waveform diagrams of sampling pulses and spike noise. In the figure, 1 is the sampled signal source, 2 is the input buffer circuit,
3 is a switch, 4 is a capacitor, 5 is an output buffer circuit, 11 is a parallel time constant circuit, 12 is a switch, 13 is a capacitor, 14 is a buffer circuit, 15 is an inverting amplifier, 16
indicates a coupling capacitor. ′
Claims (1)
ングホールド回路と、第２のサンプリングホールド回路
を設け、前記第１のサンプリングホールド回路には少な
くとも人力バッファ回路を介して被サンプル信号源が接
続され、前記第２のサンプリングホールド回路の入力端
には前記入力バッファ回路の出力インピーダンスに相当
するインピーダンスを接続し、前記第１、及び第２のサ
ンプリングホールド回路の出力を互いに逆相に接続した
ことを特徴とするサンブリレグホールド回路。A first sampling and holding circuit driven by the same sampling pulse and a second sampling and holding circuit are provided, and a sampled signal source is connected to the first sampling and holding circuit via at least a manual buffer circuit. An impedance corresponding to the output impedance of the input buffer circuit is connected to the input terminal of the second sampling and holding circuit, and the outputs of the first and second sampling and holding circuits are connected in opposite phases to each other. Sanbri leg hold circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13987281U JPS5848100U (en) | 1981-09-22 | 1981-09-22 | Sampling hold circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13987281U JPS5848100U (en) | 1981-09-22 | 1981-09-22 | Sampling hold circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5848100U true JPS5848100U (en) | 1983-03-31 |
Family
ID=29933052
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13987281U Pending JPS5848100U (en) | 1981-09-22 | 1981-09-22 | Sampling hold circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5848100U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01144299A (en) * | 1987-11-30 | 1989-06-06 | Toshiba Corp | Sample-and-hold circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56107398A (en) * | 1980-01-17 | 1981-08-26 | Trw Inc | Differential sampleeholding circuit |
-
1981
- 1981-09-22 JP JP13987281U patent/JPS5848100U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56107398A (en) * | 1980-01-17 | 1981-08-26 | Trw Inc | Differential sampleeholding circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01144299A (en) * | 1987-11-30 | 1989-06-06 | Toshiba Corp | Sample-and-hold circuit |
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