JPS584825B2 - Hand tie souchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides two transistors (hereinafter abbreviated as Tr), one in the horizontal direction and the other in the vertical direction, which have mutually different polarities.

) to constitute a logic circuit.

In recent years, unlike conventional logic circuits such as DTL, TTL, and CML, logic circuits that have a simpler structure, higher manufacturing yield, improved integration, and lower power consumption have attracted attention.

For example, in the vertical direction T that acts as an inverter element on a semiconductor substrate
r and a lateral Tr that injects minority carriers into the base region of this Tr, and attempts to effectively control the collector output by controlling the input while injecting the minority carriers into the base region of the inverter Tr. There is something.

The structure of this logic element will be explained with reference to the sectional view in FIG.

For example, an N conductivity type epitaxial layer 2 having a lower impurity concentration than this semiconductor substrate 1 is laminated on an arbitrary semiconductor substrate 1 having an N conductivity type by a vapor phase growth method, and a P conductivity type region 3,
4 is formed by selectively diffusing boron at about 1017 to 1019 atoms/cm3.

This P conductivity type region 3 has 1018 to 1021 atoms.
/cm3 of phosphorus is diffused to form an N conductivity type region 5.

The impurity concentration of the epitaxial layer 2 is lower than that of the P conductivity type regions 3 and 4.

As a result, a lateral force direction PNPTr is obtained in which the P conductivity type region 4 is an emitter region, the epitaxial layer 2 is a base region, and the P conductivity type region 3 is a collector region. A base region and a vertical NPNTr with N conductivity type region 5 as a collector region are formed.

Here, if a forward voltage is applied to the PN junction formed from the P conductivity type region 4 and the epitaxial layer 2, holes will be injected from this region 4 through the epitaxial layer 2 into the P conductivity type region 3. be done.

FIG. 2 shows an equivalent circuit of this logic element, where Ep is a constant current source connection terminal, B is a signal input terminal, C is an output terminal, and EN is a ground terminal.

Now, when the input signal of terminal B is at "1" level (for example, 0.7 volts), the external emitter current IHP injected from terminal EP has a base ground current amplification rate α of lateral force direction PNPTr.
PNP times that is, IEP×αPNP, and flows to the P conductivity type region 3, which is the collector region of this Tr and the base region of the vertical NPNTr.

Therefore, the vertical NPNTr is turned on, and the output of the terminal C becomes the "0" level.

Furthermore, the collector output current generated at this output terminal C increases the base current of the longitudinal NPNTr by its current amplification rate βNPN.
Up to the multiplied value is allowed.

Conversely, when the input signal at terminal B is at the "0" level (for example, O volts), the external emitter current IBP injected from terminal EP flows to input terminal B and does not become the base current of the vertical NPNTr. Therefore, the vertical NPNTr is turned off, and the output of the terminal C becomes "1" level.

In this way, logic elements with inverter characteristics where the input and output signal levels are mutually inverted can be combined into NAND, NO
It is possible to configure basic logic circuits such as R, FUP, FLOP, etc., and it also makes it possible to realize high-density integrated circuits with more complex functions.

The power consumption of such a logic element is greatly influenced by the characteristics of the lateral PNPTr, that is, the base-grounded current amplification factor αPNP, and decreases as the value of αPNP approaches the ideal value 1.

Further, the maximum speed frequency characteristics, fan-out noise margin, etc. of the inverter element are influenced by the characteristics of the vertical NPNTr, especially the current amplification factor βNPN whose emitter is grounded and the gain bandwidth h.

Therefore, in this logic element, the horizontal direction PNPTr and the vertical direction NP
It is important to simultaneously increase the current amplification factor of each NTr and the gain band width fT of the NPNTr in the longitudinal force direction.

Generally, the current amplification rate of a Tr is greatly influenced by the quality of carrier injection efficiency and carrier transport efficiency.

The carrier injection efficiency indicates how many minority carriers are injected from the emitter region to the base region for a unit input current. Current component of ■
When assuming each ep; it is expressed by the following equation.

Therefore, in order to improve the carrier injection efficiency, the impurity concentration in the emitter region is set to an appropriate ratio to that in the base region, and the emitter-base junction interface has an appropriate impurity concentration gradient. What is necessary is to increase the number of carriers injected into the base region and apply an accelerating electric field in the positive direction to the injected carriers.

On the other hand, the transport efficiency of carriers within the base region is expressed by the following equation, assuming the carrier diffusion distance Lb within the base region and the width W of the base region.

Therefore, in order to improve the transport efficiency of carriers, the effective distance for the carriers injected from the emitter region to reach the collector region, that is, the base width W, should be made as narrow as possible, and the carriers should be It is important to prevent the recombination center in the base region from being captured and lost.

By the way, in the structural element shown in FIG. 1, it is relatively easy to set the ratio of the impurity concentrations of the emitter region 4 and the base region 2 of the lateral PNPTr to an appropriate value and to lower the density of recombination centers in the base region. It can be done easily.

However, narrowing the base width in order to improve carrier transport efficiency is greatly restricted by photoetching technology, especially mask accuracy, and at present, the technical limit is 5 to 10 μm, so there is a certain limit. .

Furthermore, since both the emitter region and the collector region are composed of P-conductivity type impurity diffusion regions 4 and 3 which are diffused and formed opposite to the N-conductivity type epitaxial layer 2, the opposing diffusion side surfaces of both sides widen toward the end in the depth direction. go far away.

Therefore, inside the N-conductivity type epitaxial layer 2,
The deeper the diffusion, the more the two opposing P conductivity type regions 4, 3
The width of the base formed between them increases rapidly.

Therefore, the wider the bonding area is, the wider the base width is, and the transport efficiency of carriers is significantly degraded.

Furthermore, in the entire junction area between the emitter region 4 and the base region 2, as mentioned above, the P conductivity type impurity is diffused so as to be far away from the side surfaces of the opposing regions in the depth direction, so the impurity concentration gradient is extremely gentle. , carrier injection efficiency is poor.

Therefore, it is very difficult to obtain a high current amplification rate for the lateral PNPTr in the conventional structure.

Furthermore, in the conventional vertical NPNTr having the structure shown in FIG. 1, the N-conductivity type epitaxial layer 2 is used as the emitter region K, and the double diffusion layer formed therein is used as the pace region and the collector region. Although it is relatively easy to narrow the base width, the impurity concentration in the emitter region must be lower than that in the base region.

Furthermore, carriers injected into the base region are subjected to a decelerating electric field due to the impurity concentration gradient, which reduces injection efficiency and prevents so-called reverse operation in which the N-conductivity type epitaxial layer 2 is used as an emitter region. Current amplification rate is extremely low.

Furthermore, in this logic element, parts of the horizontal PNPTr and vertical NPNTr regions are merged with each other, so
Even if the impurity concentration ratio is set so as to further increase the current amplification rate of one Tr, this results in a worse result for the current amplification rate of the other Tr.

For example, in an attempt to improve the carrier injection efficiency of a lateral PNPTr, the base region, that is, the N-conducting type epitaxial layer 2
When the impurity concentration of is lowered, the carrier injection efficiency of the vertical NPNTr becomes significantly worse because the N-conductivity type epitaxial layer 2 is also the emitter region of the vertical NPNTr.

As is clear from the above explanation, the gain band width fT of this vertical NPNTr is still low due to the low current amplification rate and the fact that the emitter region is composed of the entire N-conducting type epitaxial layer 2. I could only get value.

These various drawbacks suggested that there were certain limits to the low power consumption and high speed performance of this logic element, and in particular made it clear that operation in a high frequency region was almost impossible.

The present invention eliminates the above-mentioned drawbacks and provides an improved semiconductor device.First, by improving the current amplification rate of the transistor serving as a power source and load, power consumption is reduced; The present invention simultaneously improves the forward and reverse current amplification factors of the Tr, which serves as an inverter element, to prevent the current hocking phenomenon, and to increase the speed and frequency of the element.

That is, the present invention provides a barrier layer of the other conductivity type provided in the depth direction from the surface of the semiconductor substrate of the one conductivity type, a blocking layer of the other conductivity type connected to the bottom region of the barrier layer and demarcating a substrate separation region within the substrate;
A conductivity type region is formed inside the weir layer and serves as an emitter region of a lateral Tr, with the isolation region as the collector region and the weir layer as the base region, and a conductivity type region is formed inside the substrate separation region and serves as the base region for isolation. Vertical direction T with layer as emitter region
the other conductivity type region which becomes the collector region of r, and the longitudinal direction Tr
A base connection region and a one conductivity type carrier extraction region provided in the base region and connected to each other by electrodes, and one or more metal-semiconductor rectifying contact diodes formed on the surface of the vertical Tr base region. Found in semiconductor devices.

In this invention, one conductivity type semiconductor substrate may be either P conductivity type or N conductivity type.

The substrate may be integral or may be one layer of a laminate, such as a vapor growth layer formed on a substrate.

The other conductivity type blocking layer is a layer that forms a PN junction with one side of the one conductivity type substrate, and has a higher concentration than the one conductivity type substrate,
Usually, the concentration is the same as that of the other conductive type weir layer, or the concentration is higher.

The weir layer of one conductivity type reaches the blocking layer of the other conductivity type and has a higher concentration than the substrate of one conductivity type.

The substrate separation region refers to a portion of one conductivity type region of the substrate surrounded by a weir layer of the other conductivity type and a barrier layer of the other conductivity type.

In such a semiconductor device of the present invention, the weir layer is used as a base region, the emitter region is formed within this weir layer, and the isolation region is used as a collector region.The lateral Tr isolation region is used as a base region, and a collector region is formed within this isolation region. a second longitudinal Tr formed and having a blocking layer as an emitter region; a base connection region and a base region immediately below an electrode that is provided in the base region of the longitudinal Tr and may be either a special electrode or a base electrode; A carrier extraction region of opposite conductivity type and a metal-semiconductor rectifying contact diode provided in the base region of the vertical Tr are also provided.

Therefore, in the lateral Tr, the injection efficiency of carriers from the emitter region to the base region is significantly improved, and furthermore, since an accelerating electric field is applied to the carriers, a high current amplification rate is realized.

On the other hand, in the vertical direction Tr, it is possible to set an appropriate impurity concentration ratio between the collector region, the base region, and the blocking layer which is the emitter region and is placed facing the collector region.
Further, since the impurity concentration in the base region is approximately constant, the current amplification factor in the forward direction operation in which the blocking layer is used as the emitter region can take a high value over a wide current range.

Here, the fact that the current amplification factor in the forward direction operation is sufficiently high indicates that the high speed performance, fan-out, noise margin, etc. of this logic element are significantly improved compared to conventional ones.

In addition, being able to set the current amplification factor of the reverse operation in which the other conductivity type region in the isolation region is performed as an emitter region to an appropriate value is a problem in the hogging of the input current due to the so-called large number of fine gates, which was a problem in DCTL circuits. This means that the device can be completely prevented from accumulating excess minority carriers, and the speed of the device can be increased by combining this with the presence of the carrier sucking region short-circuited with the base region.

Further, since a metal-semiconductor rectifying contact diode is incorporated, the logical amplitude of the vertical Tr increases the speed of the downward operation by the forward voltage thereof.

Furthermore, if a plurality of diodes and a plurality of vertical mTr collector regions are provided, this element becomes a multi-input multi-output NA
Since it is equipped with an ND function, the degree of integration is improved.

In this case, the numbers of diodes and collectors may or may not correspond.

Examples will be described below.

A cross-sectional view of this example is shown in FIG. 3, and an equivalent circuit diagram is shown in FIG.

For example, an N conductivity type silicon substrate used as a blocking layer in FIG. 3 forms a low concentration P-conductivity type or π conductivity type substrate 12 used as a semiconductor substrate on a high concentration N0 conductivity type substrate 11.

In order to make the impurity concentration of the substrate 12 significantly lower than that of the blocking layer 11, the impurity concentration is set to, for example, 10l4 to 1016 cm-3,
Boron is added as a P conductivity type impurity.

The substrate 12 is formed on the barrier layer using a conventional silicon epitaxial growth method, and has a thickness of, for example, 2 to 5 μm.

Next, a silicon dioxide film is deposited as an insulating film on the surface of the base 12 in a normal high-temperature oxidation atmosphere, and photoetching is performed to form a weir layer 13 that will become the base region of the transverse force direction Tr. A silicon film is perforated in a predetermined pattern.

In this state, a silicon dioxide film doped with phosphorus is grown on the surface of the substrate in a vapor phase at a low temperature of about 500° C., and thermally diffused in a non-oxidizing atmosphere to form an N-conductivity type weir layer 13.

Here, the diffusion is carried out at approximately 1200° C. so as to penetrate through the substrate and reach the blocking layer.

Further, the concentration of the weir layer is set to be 1016 to 1017 cm-3, which is higher than that of the substrate.

As a result, the substrate separation region 12' is delimited by the weir layer and the barrier layer.

Photoetching is performed again to open holes in the silicon dioxide film to expose a portion of the surface of the storage layer and another portion of the surface of the substrate separation region, and boron is thermally diffused through the openings in a high-temperature oxidizing atmosphere.

Due to this diffusion, the P-type emitter region 14 of the lateral Tr
and a P-type base connection region 18 are formed.

Although the base connection region is formed at the same time as the emitter region of the lateral transistor here, it is also possible to form it in a separate process.

Further, instead of using the co-diffusion method, the regions may be formed using another method such as an ion implantation method.

Next, in order to form multiple collector regions and one carrier suction region in the vertical direction Tr, holes are formed in a portion of the silicon dioxide layer above the substrate separation region, and phosphorus is thermally diffused in a high temperature oxidizing atmosphere.
Conductivity type regions 151, 152, and 19 are formed.

That is, regions 151 and 152 are collector regions, and region 19 is a carrier suction region and is provided so as to be short-circuited with the base connection region 18 provided previously.

Opening U holes 101, 102, 103, 104 and 301, 302, 303 are provided as desired to take out the electrodes from the insulating layer on the surface of each of these regions.

However, it is necessary that the opening 101 be opened across both the N-conductivity type carrier suction region 19 and the P-conductivity type base connection region 18 .

Next, electrode wiring is formed using a known wiring technique to form the electrode 10.
2' and 103' are connected to the output terminals B1 and B2, and 104' is connected to the power supply terminal EP, respectively, and the N conductivity type carrier extraction region 19 and the base connection region 18 are short-circuited by 101'.

Moreover, each electrode 3 provided in the perforation portions 301, 302, 303
01, 302, and 303 constitute cathodes of diodes 121, 122, and 123, respectively, whose anodes are on the substrate separation region 12' side.

The number of diodes installed is three in this example, but it may be one or more.

The electrode metal may be titanium, platinum, aluminum, etc.

And each electrode 301', 302, 303 is an input terminal A1
, A2, and A3, respectively.

However, the forward voltage of the diode incorporated in the input terminal section must be configured to be lower than the forward voltage of the emitter-base junction of the vertical NPNTr.

In FIG. 4, EP is a power supply terminal connected to the emitter region of the horizontal PNPTr, A1, A2, A3 are input terminals connected to the collector region of the horizontal PNPTr, that is, the base region of the vertical NPNTr, and B1, B2 is an output terminal connected to the collector region of the vertical NPNTr, and En is a ground terminal connected to the base region of the lateral force direction PNPTr and the emitter region of the longitudinal force direction NPNTr, respectively.

First, set the terminal En to zero potential, and add 0.7 to the terminal EP.
When a voltage is applied, the horizontal PNPTr is activated, and the holes injected from the emitter region 14 to the base region 13 pass through this region to the collector region 12', that is, the vertical direction N.
The base region of PNTr is reached.

In the vertical NPNTr, electrons are newly injected from the emitter region 11 of the vertical NPNTr to the base region 12 due to the excess holes injected into the base region.

In other words, the emitter-base junction of the vertical NPNTr is forward-biased and becomes operational, and its output terminals B1, B
The potential at point 2 is almost zero potential.

However, at this time, the input terminals A1, A2, and A3 are in an open state, or are in a state where an appropriate positive voltage higher than the threshold voltage of the vertical NPNTr with the emitter grounded is applied.

Further, when at least one of the input terminals A1, A2, and A3 is set to zero potential, the vertical NPNTr is cut off, and the output terminals B1 and B2 are set to a positive potential.

In other words, a multi-input multi-output NAND function logic element is constructed in which the output is "0" only when all the inputs are "1".

It is obvious that the plurality of rectifying diodes have an AND function, and the vertical NPNTr part has an inverter function.

Incidentally, in the above description, the semiconductor substrate is of P conductivity type and starts from P type, but it is of course possible to start from N conductivity type.

Therefore, in this case, if the conductivity type and power source of each region and layer are all reversed, the device will operate in the same way.

In such a new logic element, the base width of the lateral transistor that serves as a current source and load can be controlled by diffusion, without depending on the mask width as in conventional lateral transistors, so it can be made extremely narrow, and carriers can be controlled from the impurity profile. On the other hand, since an accelerating electric field is applied, carrier injection efficiency and transport efficiency are significantly improved.

Therefore, a high current amplification rate can be obtained over a wide current range, and power consumption as a logic circuit is significantly reduced.

Furthermore, since a vertical transistor with the blocking layer 11 as an emitter is used as an inverter element, it is possible to realize a high current amplification rate over a wide current range as well as a high gain band width ∫
You can get T.

Furthermore, due to the presence of a carrier extraction region short-circuited to the base region of the longitudinal NPNTr, excessive minority carriers accumulated in the base region and collector region can be suppressed, making it possible to increase the output reversal speed. A metal-semiconductor rectifying contact diode, which has a forward voltage characteristic lower than the forward voltage of the emitter-base junction of a vertical transistor having an inverter function, is formed on the anode side by the base region of the vertical transistor itself. Output NAND
It also has the effect of realizing functions with a single element.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a conventional semiconductor device, FIG. 2 is an equivalent circuit diagram of the device shown in FIG. 1, and FIG. 3 is a sectional view of a semiconductor device of the present invention.
FIG. 4 is its equivalent circuit diagram. In Fig. 3, 12...base body, 13...weir layer, 12...
-Substrate separation region, 11...blocking layer, 14...lateral direction T
r emitter region, 151, 152... collector region of vertical Tr, 18... base connection region, 19...
・Carrier suction area, 121, 122, 123...
diode.

Claims (1)

[Claims] 1. A weir layer of the other conductivity type provided in the depth direction from the surface of the semiconductor substrate of the one conductivity type, a blocking layer of the other conductivity type connected to the bottom region of the weir layer and demarcating a substrate separation region within the substrate, and a barrier layer of the weir layer. A conductivity type region is formed inside the substrate isolation region and serves as the emitter region of a lateral transistor in which the isolation region is the collector region and the weir layer is the base region. A region of the other conductivity type that serves as the collector region of the vertical transistor as a region, a base connection region and a carrier extraction region of one conductivity type provided in the base region of the vertical transistor and connected to each other by electrodes, A semiconductor device comprising one or more metal-semiconductor rectifying contact diodes formed on the surface of a base region.