JPS5848459A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5848459A JPS5848459A JP56145857A JP14585781A JPS5848459A JP S5848459 A JPS5848459 A JP S5848459A JP 56145857 A JP56145857 A JP 56145857A JP 14585781 A JP14585781 A JP 14585781A JP S5848459 A JPS5848459 A JP S5848459A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor
- metal layer
- nitride layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、特に半導体装置の電極構造に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention particularly relates to an electrode structure of a semiconductor device.
高信頼6度半導体装置、特にバイポーラトランジスタ、
ダイオード等の電極には、耐熱性、耐マイグレーシ、ン
破壊性、耐腐食性等が要求される。Highly reliable 6 degree semiconductor devices, especially bipolar transistors,
Electrodes such as diodes are required to have heat resistance, migration resistance, destruction resistance, corrosion resistance, etc.
このため、第1図に模式的に示した様なTi−Pt−A
u構造の電極が採用されている。電子回路素子が形成さ
れるシリコン1にはその表面にすでに白金シリサイド等
のオーミ、り接触を得る金属が形成されて諭るものとす
る。ここでTi層2社、シリコン1の他の部分に4形成
されその上に配線が形成される8i0.勢の5表面保賎
膜との密着性及びシリコン1中へのPt3の侵入に対す
る障、壁効果のためのものであJ)、Pt層3はA u
4とTi2との合金化を防ぐ障壁効果のためのもので
Toシ、またAu層4は電流の導体として及び保護膜と
してのものである。For this reason, Ti-Pt-A as shown schematically in Fig.
U-structured electrodes are used. It is assumed that the silicon 1 on which the electronic circuit element is formed has already had a metal such as platinum silicide formed thereon to obtain ohmic contact. Here, 2 Ti layers are formed on other parts of the silicon 1, and 8i0. The Pt layer 3 is for adhesion with the protective film on the surface of the layer 5 and for the barrier and wall effect against the penetration of Pt3 into the silicon 1).
The Au layer 4 serves as a current conductor and as a protective film.
しかし第1図の様なT i −P t −Au構造の電
極を用いた場合でも、高温下において電極構成金属のシ
リーン層への侵入が避けられず、十分な耐熱性を得るこ
とが困難であった。また第1図の電極の場合、Tl−P
t界面に合金層ができ、この合金層が電極形成時のエツ
チングに困難さを伴うことがあった。However, even when using an electrode with the Ti-Pt-Au structure as shown in Figure 1, it is difficult to avoid the penetration of the electrode constituent metal into the silane layer at high temperatures, making it difficult to obtain sufficient heat resistance. there were. In addition, in the case of the electrode in Fig. 1, Tl-P
An alloy layer is formed at the t-interface, and this alloy layer may be difficult to etch during electrode formation.
本発明の目的は、高温下でも電極構成金属の半導体への
侵入がなく、又製造の容易な半導体装置を提供するもの
である。An object of the present invention is to provide a semiconductor device that does not allow electrode constituent metal to penetrate into the semiconductor even at high temperatures and is easy to manufacture.
本発明による半導体装置は、その電極構成として半導体
基板と良導電性金属層との間にTi層の遷移金属の窒化
物層を有しておシ、このTi等の遷移金属の窒化物層に
よって、下地半導体層への上部良導電性金属層構成金属
の侵入を防止しした半導体装置を得る。The semiconductor device according to the present invention has a transition metal nitride layer such as a Ti layer between a semiconductor substrate and a highly conductive metal layer as its electrode structure. Thus, a semiconductor device is obtained in which the metal constituting the upper highly conductive metal layer is prevented from entering the underlying semiconductor layer.
以下、本発明を図面を参照してよシ詳細に説明する。Hereinafter, the present invention will be explained in detail with reference to the drawings.
本発明の一実施例としてのバイポーラトランジスタの断
面図である第2図a、bを参照すると、まず、第2図a
に示す様に、半導基板もしくはエピタキシャル層である
コレクタ領域5にペース領域6及びエミッタ領域7を形
成する。シリコン酸化層等の表面保11J[12K[極
取シ出し用の開孔を設けた@ptの蒸着し、熱処理によ
って各領域と合金化し、Ptシリサイド層8を形成する
。表面保饅膜12上等の未反応ptは除去される。その
後、低圧のN、とArの混合ガス、例えば混合比1:5
中でTiを100〜1ooou程度反応性スパッタリン
グすることにより、Tiの窒化物層9を形成する。その
上に%ptpt層をスパッタリングまたは蒸着により、
Au層11を同様に蒸着等により形成する。次に第2図
すに示す様に7オトレジスト等(図示せず)をマスクと
して、イオンミーリング法等によシ選択的に除去してT
l窒化物9−Pt1O−Aull構造の引出し電極形成
を行なう。Referring to FIGS. 2a and 2b, which are cross-sectional views of a bipolar transistor as an embodiment of the present invention, first, FIG.
As shown in FIG. 2, a space region 6 and an emitter region 7 are formed in a collector region 5 which is a semiconductor substrate or an epitaxial layer. A Pt silicide layer 8 is formed by depositing a surface layer such as a silicon oxide layer 11J [12K] with an opening for removing the electrode and alloying it with each region by heat treatment. Unreacted PT on the surface protective film 12 and the like is removed. Then, use a low-pressure mixed gas of N and Ar, for example, at a mixing ratio of 1:5.
A Ti nitride layer 9 is formed by reactive sputtering of about 100 to 1000 Ti. By sputtering or evaporating a %ptpt layer thereon,
The Au layer 11 is similarly formed by vapor deposition or the like. Next, as shown in Figure 2, using a mask such as 7-otoresist (not shown), selectively remove it by ion milling or the like.
An extraction electrode having a nitride 9-Pt1O-Aull structure is formed.
菖2図すのように、Tl窒化物9を半導体とPt10や
Au11等の良導電体との間に配置した電極構成とする
ことで、組成の緻密なTiの窒化物層9によ6、pt層
10のエン、夕領域7及びペース領域6への拡散に対す
る障壁効果がよシ一層大きくなシ、耐熱性の優れたバイ
ポーラトランジスタを得23ヒとができる。従って、高
温下において屯トランジスタ等の電気的特性の変動が少
なく、十分な寿命を有する超高信頼度素子を得ることが
できる。 □
またTIの窒化物層9は安定で、Pt層lOとの反応は
起シに〈<、電極加工にウェ、トエ、チングを用いた場
合でも容易に加工できる。As shown in Figure 2, by forming an electrode structure in which the Tl nitride 9 is placed between the semiconductor and a good conductor such as Pt10 or Au11, the Ti nitride layer 9 with a dense composition can The barrier effect of the PT layer 10 against diffusion into the back region 7 and the space region 6 is even greater, and a bipolar transistor with excellent heat resistance can be obtained. Therefore, it is possible to obtain an ultra-high reliability element that exhibits little variation in the electrical characteristics of a transistor or the like under high temperatures and has a sufficient lifespan. □ Furthermore, the TI nitride layer 9 is stable and does not react with the Pt layer 1O, and can be easily processed even when using a wafer, a toe, or a etch for electrode processing.
ζζではバイポーラトランジスタについて説明したが、
ダイオード、電界効果トランジスタ及びそれらの素子を
含むモノリシック集積回路についても同様に本発明が実
現可能なことは言うまでもない。またTiの窒化物9の
かわシにW、Mo。In ζζ, we explained bipolar transistors, but
It goes without saying that the present invention is similarly applicable to diodes, field effect transistors, and monolithic integrated circuits containing these elements. In addition, W and Mo were added to the Ti nitride 9.
Cr等の遷移金属の窒化物を用いても同様の効果が期待
される。Similar effects can be expected by using nitrides of transition metals such as Cr.
第1図は従来構造の電極を示す断面図、第2図a及び第
2図すは本発明の一実施例を製造工程順に示した断面図
である。FIG. 1 is a cross-sectional view showing an electrode of a conventional structure, and FIGS. 2a and 2 are cross-sectional views showing an embodiment of the present invention in the order of manufacturing steps.
Claims (3)
1の金属層と、核第1の金属層に接触する遷移金属の窒
化物からなる第2の金属層と、咳第2の金属層上に形成
された良導電性の第3の金属層とを有する仁とを特徴と
する半導体装置。(1) a semiconductor region, a first metal layer in resistive contact with the semiconductor region, a second metal layer made of a transition metal nitride in contact with the first metal layer, and a second metal layer; and a highly conductive third metal layer formed on the layer.
る特許請求の範囲第1項記載の半導体装置。(2) The second metal layer is titanium or tungsten. The semiconductor device according to claim 1, which is a nitride of a metal selected from molybdenum and chromium.
第2の金属層はチタン窒化物であシ、前記第3の金属層
は前記第2の金属層に接触する白金とこの白金に接触す
る金との多層構造をしていることを特徴とする特許請求
範囲第1項記載の半導体装置。(3) The first metal layer is made of platinum silicide, the second metal layer is made of titanium nitride, and the third metal layer is made of platinum in contact with the second metal layer. 2. The semiconductor device according to claim 1, wherein the semiconductor device has a multilayer structure with gold in contact with the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56145857A JPS5848459A (en) | 1981-09-16 | 1981-09-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56145857A JPS5848459A (en) | 1981-09-16 | 1981-09-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5848459A true JPS5848459A (en) | 1983-03-22 |
Family
ID=15394680
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56145857A Pending JPS5848459A (en) | 1981-09-16 | 1981-09-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5848459A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6293183A (en) * | 1985-06-25 | 1987-04-28 | Mirai Ind Co Ltd | Delivery method for flexible conduit pipe and guide member therefor |
| JPS6279760U (en) * | 1985-11-07 | 1987-05-21 | ||
| JPS62272557A (en) * | 1986-03-29 | 1987-11-26 | フィリップス エレクトロニクス ネムローゼ フェンノートシャップ | Manufacture of semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS507430A (en) * | 1973-05-18 | 1975-01-25 | ||
| JPS5024596A (en) * | 1973-02-20 | 1975-03-15 | ||
| JPS5271174A (en) * | 1975-12-10 | 1977-06-14 | Fujitsu Ltd | Production of semiconductor device |
-
1981
- 1981-09-16 JP JP56145857A patent/JPS5848459A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5024596A (en) * | 1973-02-20 | 1975-03-15 | ||
| JPS507430A (en) * | 1973-05-18 | 1975-01-25 | ||
| JPS5271174A (en) * | 1975-12-10 | 1977-06-14 | Fujitsu Ltd | Production of semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6293183A (en) * | 1985-06-25 | 1987-04-28 | Mirai Ind Co Ltd | Delivery method for flexible conduit pipe and guide member therefor |
| JPS6279760U (en) * | 1985-11-07 | 1987-05-21 | ||
| JPS62272557A (en) * | 1986-03-29 | 1987-11-26 | フィリップス エレクトロニクス ネムローゼ フェンノートシャップ | Manufacture of semiconductor device |
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