JPS5848B2 - Micro program guide - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a microprogram control device that controls the execution of a microprogram in a microprogram-controlled data processing device.

The microprogram control device in a microprogram-controlled data processing device is designed to have a large number of configuration bits so that as much control information as possible can be controlled at the same time when the emphasis is on high processing speed of the data processing device. When controlling micro-instructions, if the emphasis is on reducing the cost of the data processing device rather than on processing speed, micro-instructions with a small number of constituent bits are used so that the storage capacity for accommodating the microprograms is small. It is normal to control the

Conventional microprogram controllers can control only one type of microinstruction group, depending on the emphasis placed on the data processing device.

In other words, the microprogram control device of a data processing device with an emphasis on cost reduction cannot be used in a data processing device with an emphasis on high processing speed.
The same can be said for the opposite case.

However, considering that LSI microcomputers are used as microprogram control devices for data processing equipment, a microprogram control device that is compatible with both types of data processing equipment is required. .

Therefore, the main objects of the present invention are to provide a data processing device that increases processing speed by increasing the number of bits constituting a microinstruction, and a storage device that accommodates a microprogram by reducing the number of bits that constitute a microinstruction. Our objective is to provide a microprogram controller that is compatible with both data processing equipment and data processing equipment with reduced capacity.

The microprogram control device according to the present invention uses a fixed-length microinstruction structure that includes a first microinstruction group and a second microinstruction group, each of which is composed of one-word microinstructions and can operate simultaneously. A first microprogram consisting of microinstructions in units of one word and a second microprogram consisting of a couple of the first microinstruction group and the second microinstruction group are selectively executed. First and second microinstruction registers that accommodate microinstructions in units of words; and only when the microinstruction stored in the first microinstruction register is a microinstruction of the first microinstruction group, the microinstruction is processed. a first decoder that outputs a control signal to execute the microinstruction, and a second decoder that outputs a control signal to execute the microinstruction only when the microinstruction stored in the microinstruction register is a microinstruction of the second microinstruction group. and a second decoder that stores the microinstructions of the first microprogram in each of the first and second microinstruction registers when executing the first microprogram, and executes the second microprogram. Sometimes the microinstructions of the first and second microinstruction groups are stored in the first and second microinstruction registers, respectively.

The present invention provides a means for sorting microprograms consisting of microinstructions with different numbers of constituent bits as described above, and selectively controlling the execution of these microprograms. It provides a control device.

Therefore, at the stage of this invention, a first storage device that accommodates a microprogram made up of microinstructions in units of 1 word, and a microprogram made up of microinstruction couples in units of 2 words are provided. There is no limitation on the means for selectively coupling either of the second storage devices and the microprogram control device according to the present invention.

In detail, this combination can be done manually or as described in the patent application to be filed later.

Next, embodiments of this invention will be described with reference to the drawings.

Referring to Figure 1, the microinstruction group used in the microprogram control device according to the present invention is such that, in the example shown in this figure, each microinstruction consists of one 16-bit word.

Bits 0 and 1 give the operation code (OP).

When OP is 00, it represents a branch instruction; when OP is another code, ie, 01, 10°, or 11, it represents register operation instruction 1, 2, or 3.

Among the combinations of 2-word microinstructions created by these microinstructions, the only ones that can operate simultaneously are branch instructions and register operation instructions with OPs of 01, 10, and 11. Suppose that there are only successive combinations with one of the following.

Referring to FIG. 2, in all of these possible combinations, microinstruction couples, the first word M11 of the couple has a branch instruction with OP 00, and the second word MI2 has an OP 01, 10, or 1
There are 1 register operation instructions.

Referring to FIG. 3, the main part of the embodiment of the device according to the invention, namely the part controlling the execution of the microinstruction groups and the microinstruction couples, includes a first microinstruction block containing the first word of the microinstruction couples. instruction register 11
and a second microinstruction register 1 containing a second word.
2, and a branch instruction decoder 16 for decoding the microinstructions stored in the first microinstruction register 11.

The branch instruction decoder 16 assumes that a microinstruction with an OP of 00 is a branch instruction, and outputs control signals necessary for a branch operation to a plurality of branch operation control conductors 17.
Or for 11 microinstructions, it simply prompts the update of the sequence counter (not shown).

The apparatus of this embodiment further includes a register operation instruction decoder 18 for decoding the microinstructions contained in the second microinstruction register 12.

The register operation instruction decoder 18 assumes that the microinstructions with OPs 01, 10, and 11 are register operation instructions, and decodes the respective registers (
A plurality of register operation control conductors 1 carry control signals necessary for register operation (not shown).
9, but the control signal is controlled so that no register operation is performed for microinstructions with OP of 00.

Referring to FIG. 4, when it is desired to execute a microprogram composed of one-word microinstructions, the first storage device 21 containing this program is transferred to the microprogram control device according to the present invention. 4 Connect as shown in Figure A.

The one word microinstruction read from the storage device 21 is stored in the first and second microinstruction registers 11 and 1.
2 are set the same for both.

When the OP of this microinstruction is 00, the branch instruction decoder 16 causes the branch operation to be executed in the data processing device, but the register operation instruction decoder 18 does not execute the register operation.

When the OP of this microinstruction is 01, 10, or 11, the register operation instruction decoder 18 operates to execute the register operation, but the branch instruction decoder 16 only advances the sequence counter by one step. .

In this way, microinstructions read in 1-word units execute branch instructions or register operation instructions in 1-word units.

Next, when you want to execute a microprogram consisting of a couple of microinstructions in units of 2 words,
A second storage device 22 containing this microprogram is coupled to the microprogram controller according to the invention, as shown in FIG.

The first word M11 and the second word MI2 of the two-word microinstruction couple read from the storage device 22 are the first and second microinstruction registers 11 and 12.
are set respectively.

Branch instruction and register operation instruction decoders 16 and 18 each decode corresponding instructions so that they operate independently and simultaneously.

In this way, the microinstruction couple read in units of 2 words executes simultaneous operations in units of 2 words.

[Brief explanation of the drawing]

FIG. 1 shows an example of a microinstruction group in units of one word, FIG. 2 shows an example of a microinstruction couple group that can be handled by the microprogram control device according to the present invention, and FIG. Figure 4 is a block diagram of the main parts in the example, and is a diagram explaining the operation of the embodiment of this invention whose main parts are shown in Figure 3. In the figure, 11 and 12 are first and second instruction registers, and 16 and 18 are branch instruction and register registers.
Operational instruction decoders, 21 and 22 indicate first and second microprogram storage devices, respectively.

Claims (1)

[Claims] 1. A fixed-length microinstruction body containing a first microinstruction group and a second microinstruction group, each consisting of one-word microinstructions and capable of simultaneous operation, is used to process microinstructions in one-word units. Each microinstruction is configured to execute a microinstruction in units of one word so as to selectively execute a first microprogram consisting of a pair of microinstructions and a second microprogram consisting of a couple of a first microinstruction group and a second microinstruction group. first and second microinstruction registers to accommodate, and a control signal for executing the microinstruction only when the microinstruction accommodated in the first microinstruction register is a microinstruction of a first microinstruction group. a first decoder; and a second decoder that outputs a control signal for executing a microinstruction only when the microinstruction stored in the second microinstruction register is a microinstruction of a second microinstruction group. , when the first microprogram is executed, the microinstructions of the first microprogram are stored in the first and second microinstruction registers, respectively, and when the second microprogram is executed, the microinstructions of the first microprogram are stored in the first and second microinstruction registers. A microprogram control device in which microinstructions of an instruction group are stored in first and second microinstruction registers, respectively.