JPS5850687A - Editing device of digital signal - Google Patents

Abstract

PURPOSE:To facilitate the editing work, by storing previously both the reproduced signal and a specific address into a memory and detecting the specific address in a monitor mode to report the reference point such as an editing point, etc. CONSTITUTION:The tapes 1 and 2 are connected to terminals P1 and P2 respectively, and a tape 3 is edited with a terminal R. The data of the tape 1 is recorded cyclically to a memory 12. An editing device is set in an editing point retrieving mode through a control input part 9. The signal is fed from the part 9 at the place near the boundary between A and B of the tape 1 while monitoring a speaker 21. An accurate editing point in the memory 12 is obtained by a manual clock generator 23 and read into a CPU5 to be preserved in an RAM7. An address detector 27 lights up a lamp 28 when the contents of a counter 13 reaches the editing point. The boundary between C and D of the tape 2 is obtained in the same way. The cross fading is carried out through a cross fading processing circuit 15 for data A and D.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal editing device for editing digital signals recorded and played back by a digital recording and playback device, and in particular, it is possible to accurately and easily identify editing points, and to perform precise editing and easy processing. The present invention provides a digital signal editing device that can perform various tasks.

Traditionally, when editing analog-recorded tapes, useful parts of the recorded tapes were manually cut and spliced together.
They have been hand-cut and edited into book tapes. This situation is shown in FIG. In Figure 1, 1' and 2' are parts of different recorded tapes, 5 parts of 1' are necessary parts, part B is unnecessary part, 0 part of 2' is unnecessary part, D The part is the necessary part. A desired tape 3' can be obtained by cutting these tapes and mechanically joining them together. At this time, tape 1'.

2' cutting position, that is, the boundary between M and B and C and D (
It is necessary to find the edit point (hereinafter referred to as the edit point).
For this purpose, the following work was necessary. That is, the tape recorder is put into a playback state, and while listening to the playback sound, the tape recorder is stopped at a position that appears to be an editing point. To find a more accurate editing point, manually rotate the tape recorder's take-up reel and supply reel in the same direction, forward or backward, and then listen to the playback sound to determine the point. . That is, when such fine adjustments are made and it is determined that the tape is at a desirable editing point, the position of the tape in contact with the gap portion of the reproducing head is set as the correct editing point, and the above-mentioned cutting is performed. The reason why the tape is cut diagonally as shown in FIG. 1 is to prevent the reproduced sound from becoming discontinuous at the editing point when the edited tape is played back.

This is because the effect is that the sound of the fifth part gradually becomes quieter (fade around) and the sound of the D part gradually becomes louder (fade in). This connection processing is called a crossfade.

Such editing work is indispensable when creating music tapes, etc., but difficult problems arise when applying it to digital recording and playback devices that have been put into practical use in recent years. That is, since the recorded signal in a digital recording and reproducing apparatus is a digital signal, cutting diagonally like an analog signal means that meaningless information continues for that period. On the other hand, in order to reduce the amount of information lost as much as possible, digital recording and playback devices usually add error and correction codes to the information bits of the samples in the tape advancing direction and record them as lPCM frames.
MlPCM frames are unavoidable. Therefore, it is necessary to perform operations such as ((a) muting that part; (b) skipping that part and connecting the information before and after it.
In any case, the deterioration in the sound quality of the original information in that part is essentially a problem.

The present invention has been made in view of the above-mentioned conventional problems. 5. A digital signal that allows a desired predetermined position such as an editing point of a signal to be notified during monitor playback in the silk industry and allows editing work to be performed accurately and easily. It provides an editing device.

An embodiment of the present invention will be described below based on the drawings. First, an outline of the editing method of the digital signal editing device of the present invention will be explained. In this method, the recorded tape is not cut mechanically, but three digital recording and playback devices are used, and the playback digital signal of the first digital recording and playback device is played back up to the editing point, and then the second The digital recording/playback device switches to a playback digital signal and records it on a third digital recording/playback device to create an edited tape.

This will be explained with reference to FIG. That is, in Figure 2,
(a) is the first tape 1 attached to the first digital recording/playback device, (b) is the second tape 2 attached to the second digital recording/playback device, (C) A third tape 3 is used to record the edited digital signal, and is mounted on a third digital recording/playback device. First, the first tape loaded in the first digital recording/playback device is rewound a little beyond the starting point 4 of the required segment, and at the same time, the second tape loaded in the second digital recording/playback device is rewound. Rewind to the front by L2 from the boundary between C and D. Then, the first tape is played back, and when the starting point 4 of the first tape is reached, the third tape attached to the third digital recording/reproducing device is put into a recording state, and the first tape is recorded. Then, the first tape is moved by L1 from the boundary between M and B, and this value is equal to the time when the playback head of the first digital recording and playback device comes into contact with the boundary between M and B of the first tape. C of the second tape at the moment
It is sufficient that the length is sufficient to run the first tape and the second tape synchronously so that the playback head of the second digital recording and playback device comes into contact with the boundary between and D.

In this way, the first tape and the second tape are run synchronously, and the third tape. The digital signal to be recorded on the tape is
A third edited tape, such as C, can be created by switching from the boundary between tapes M and B to D of a second tape.

At this time, at the boundary between M and D, a d1 digital operation is performed to fade out M and fade in D. These operations are performed using time codes recorded on separate tracks on the tape.

The present invention realizes a digital signal editing device based on the above-mentioned idea, and a detailed description of the embodiments will be given below. In FIG. 3, 6 is a CPU (microcomputer) that controls this device, and 6 is a CPU 5.
ROM that stores the s program.

8 is a data bus (the address bus is omitted in the figure), 9 is an operation input section that gives control commands to this device, and q is a cptys for operation input.
A control output unit 10 is for outputting a control signal to display an indication that the device has been received or to control other parts of the device; This is an interface element for interfacing q with the CPU 6. on the other hand,
Pl.

P2 are PCM data input terminals from the first and second digital recording/recording devices (hereinafter referred to as PCtM tape recorders), respectively. 11 is a switch controlled by the output of the control output unit 9' via the interface element 10 from cptys, and 12 is the PC via the switch 11.
, M memory for writing and storing data, 13 is memory 1
2 is the address color, number 14 is the address counter 13
and OP U st - PCM data of the second PCM tape recorder input from the inter-connect terminal P1 and the input terminal P.
The second P input from 2 (3M tape recorder PC
This is a cross-fade processing circuit that digitally calculates M data to generate a cross-fade. Reference numeral 16 denotes an interpolation circuit, which prevents the clock frequency from being mixed into the reproduced audio as noise when the memory 12 is reproduced at a variable speed and the memory is read at a clock frequency lower than the original sampling frequency. belongs to. 17 is the cross-fade processing circuit 15 and the interpolation circuit 1
6 is a switch for switching either one of the outputs according to the output of a control section 9', 18 is a D/M converter, 19 is a low-pass filter, 20 is an amplifier, and 21 is a monitor speaker. The negative value is determined at the output terminal to the third PpM tape recorder (recording tape recorder). 22 is a reference clock pulse generation circuit, 23 is a manual clock pulse generator, 24
is one of the outputs of the reference clock pulse generator 22 and the manual clock pulse generator 23 as the control output m.
This is a selector switch that selects and outputs the output of W.

The TP1 terminal is an input terminal for the SMPTK time code reproduced by the first PCM tape recorder connected to the P1 terminal, 26 is a time code interface circuit that interfaces the above time code input and the CPU 6, TP2
The terminal is the second P (input terminal for SMPTX time code played on a 3M tape recorder, 2) connected to the P2 terminal.
6 is a time code interface circuit for interfacing the time code input and 0PU5.

Reference numeral 27 denotes an address detector which inputs commands from the interface element 14 to the address counter 13, and also inputs the output of the address counter 13. That is, the edit point address calculated from the initial value of the address counter 13 preset by the CPU 5 or the edit point address directly specified from the operation input section 9 is held, while the output of the address counter 13 changes. ,
When the edit point address is output, a match with the held value is detected, and the output lights up, for example, a lamp 28 of the control output section q.

Next, the operation of this embodiment will be explained based on FIG. As a premise, the tape attached to the first PCM tape recorder connected to the P1 terminal is the first tape 1 explained in FIG. 2, and the second PCM tape recorder connected to the h terminal is the same second tape A third PCM tape recorder read directly to the R terminal is also called a third tape 3.

Each of them is referred to as a playback tape recorder L1, a playback tape recorder M1, and a recording tape recorder. Figure 2 (
To make the third tape shown in FIG. 0), firstly, edit the editing points, that is, the starting point 4 of the first tape shown in FIG. O, D of tape
We need to find the exact location of the boundary.

Next, the operation for determining the editing point will be explained.

First, in order to determine the starting point 4 of the first tape, the playback tape recorder L plays back the portion of the first tape before point 4, and
Input to 1 terminal. At this time, switch 11 turns g-h ON.
When PCM data is input to the P+ terminal, this data is cyclically recorded in the memory 12 via the switch 11. In other words, when writing is completed to the last address of the memory 12, writing starts again from the first address, and as a result, if we take a certain moment,
The PCM data stored in the memory 12 is always continuously stored from that moment to a certain period of time ago. - the address of this memory 12 is controlled by an address counter 13; The clock pulses of the counter 13 are supplied with n clock pulses generated from the reference clock pulse generation circuit 22 by turning on e-el of the switch 24. Furthermore, switch 17 has a-b turned on,
Input PCMP'-Y is cross-fade processing circuit 1
6 and then through the switch 17 to the D/MU converter 18.
The signal is converted into the original analog signal, the high-frequency components are cut by the n% low-low-pass filter 19, the signal is amplified by the amplifier 20, and the signal is supplied to the speaker 21.
For example, the polarity of the switches 11, 17 and 24 and the D signal of the cross-fade processing circuit 16 are used. That is,
A signal from an operation input unit 9 consisting of a keyboard pushbutton, etc. is transmitted to the CPU 5 via an interface element 10 and a pass line 8, and a corresponding control signal is transmitted to the CPU 5.
This signal is output from U6 via the pass line 6 and the interface element 1o to the control output section e'. Note that in FIG. 3, control lines other than the switches from the control output section q are omitted.

The editor inputs a signal from the operation input section 9 indicating that it is time to edit while monitoring the output audio from the speaker 21. This signal is sent to the CPU via the above route.
s, and the following control is performed via the control output section q. First, the editor continues the previous operation for a certain period of time from the editing point desired, and after a certain period of time, the memory 12
Stop writing to. Thereafter, the playback side tape recorder L performs operations according to instructions from the CPU 5, but these operations are completely omitted in the figure. Now, the contents of the memory 12 at this time are as shown in FIG. Here, the specifications are assumed as follows. The audio data is 16 bits/sample, the sampling frequency is so KHz, and the memory is 2561 mW (IW=16
In this way, the audio data stored in the memory 12 is approximately 6 seconds, as -1266/501C=5 seconds. Of course, in order to save memory, the data may be stored in the memory every other sample (this means that the sampling frequency is 1 o). Alternatively, a method such as reducing the number of bits per sample using a bit compression method may be applied.

In order to simplify the explanation, we will not perform any such processing here. In FIG. 4, a 266KW memory is simulated, and audio data is sequentially written from left to right, and when it is written up to 2FFFF, it is written again from ooooo, and this is repeated. The memory address corresponding to the timing desired by the editor is represented by an X in the figure. Then, writing is completed at a timing corresponding to the Y memory address delayed by, for example, 4 seconds within the repetition cycle as a fixed period of time. As a result, the memory 12 stores (
This means that the audio is recorded in the order of Y+1)-+2FFFF-+ooooo→Y.

Next, in order to search for the correct editing point, the contents of the memory 12 are read out. 15 The editor sets the device to be in the editing point search mode from the operation input section 9, thereby sending control signals to each section. becomes as follows. switch 17
In this case, a-C are turned on, and switches 11-f of the switch 24 are turned on. , 23 is a manual clock pulse generator composed of a rotary encoder or the like, and the frequency of the pulses it generates changes depending on the speed of movement, and if it is stopped, it will not generate any pulses at all. 'For example, if a rotary dial is adopted as the manual control means.

The higher the rotation speed, the more pulses are generated. If this pulse and information on the rotation direction are given to the address counter 13 and it operates as an up-down counter, for example, when the rotation is clockwise, the address of the memory is set in the forward direction, that is, in the order of X - + Y, and the contents of the memory are set. read out. This read PCM data is interpolated by an interpolation circuit 16, and converted into the original analog signal by a D/A converter 18 via a switch 17. is cut, amplified by the amplifier 2o, and supplied to the speaker 21, where the editor monitors the sound. The faster the rotary dial is rotated, the higher the frequency of the audio to be reproduced becomes. When rotated counterclockwise, X4000
The audio is reproduced in the order of 0-+2FFFF4 (Y+1), and the sound is reproduced as if the recorded tape of a tape recorder was rotated backwards. Naturally, the frequency of the reproduced sound changes depending on the rotation speed at this time as well. 60K like this
When audio sampled and recorded at Hz is played back at a variable speed, the following problems arise. That is, there is no particular problem when reproduction is performed at a clock frequency of s o Kf (z or higher), but when reproduction is performed at a frequency lower than 50 KHz, for example 10 KHz, a 10 KHz component is generated due to this clock frequency.

However, the cutoff frequency of the low-pass filter 19 is, for example, 20
This is the optimum value when the sampling frequency is 50 KHz. Therefore, the 10 KHz component is not removed by the low-pass filter 19 and is heard as noise. In order to solve this problem, the interpolation circuit 16 is operated.

Next, the function of the interpolation circuit 1e will be explained with reference to FIG. FIG. 5(a) shows the audio signal stored in the memory reproduced at normal speed, that is, so KHz, and subjected to D/MU conversion. When the same signal is reproduced at 10 KHz and subjected to D/MU conversion, the result is as shown in FIG. 6(b). Here, Figure 6 (
The 8 points in a) and (b) indicate the same sample. The goal of this circuit is to smoothly interpolate the discontinuous portions of these signals at 50 KHz as shown in FIG. 6(q).

First, the concept of interpolation will be explained. Figure 6(b)
, (An enlarged view of a part of C1 is shown in Fig. 6. In Fig. 6, 31 is the input to the interpolation circuit. a, b are sample values of adjacent samples. TIO, T20 are manual clock pulses. At the timing of , T21T becomes Tt.

This is the timing one clock cycle after. Tlo, T.
t+.

T12, Tls, T14, 'ha are the timings of sampling clock pulses. 32 is the output of the interpolation circuit 16.

The output L1n of the interpolation circuit 16 at Tln (n=o, 1, 2, 3.4) is determined as follows.

L+n=tortoise+(ba-a) -n 11k ---
(1) Here, k is a coefficient (slope coefficient) that is inversely proportional to the frequency of the output of the manual clock pulse generator 23, for example, the sixth
In the case shown in the figure, the output of the manual clock pulse generator 23 is 10 KHz, and the sampling frequency is 5.
Since it is 0 uZ, it is set to 1A. (1) Formula % Formula % It can be seen that 32 interpolations shown in FIG. 6 can be performed.

Figure 7 shows a block cape for realizing the above functions.

FIG. 7 shows a block diagram of the interpolation circuit 16.

52 is a 16-bit parallel signal input to the interpolation circuit, -6
3 is a terminal to which the output of the manual clock pulse generator 23 is input; 64 is a sampling clock (in this case, 6oK);
Hz, ) input terminal. 41.42 is a latch circuit,
43 Huh? A subtraction circuit subtracts the output of the latch circuit 42 from the output of the child circuit 41, 44 is an addition circuit, and 46 is a latch circuit that latches the output of the addition circuit 44 using a sampling clock.

46 is a reference clock pulse generation circuit (for example, 5
0KHz x 100=5MHz clock pulse). 47 is a manual clock pulse generator 23
a counter 48idR that is reset by the output of the reference clock pulse generation circuit 46 and counts the output of the reference clock pulse generation circuit 46;
49 is a circuit that uses the output value of the counter 47 as an address and outputs the contents of the ROM corresponding to that address to generate a slope coefficient k. A circuit that multiplies the slope of the output; 60 is an adder circuit that adds the output of the multiplier circuit 49 and the output of the latch circuit 42; 61 is a polarity that latches the polarity bit of the output of the latch circuit 43 and determines the polarity of the multiplier circuit 49; It is a decision circuit. 66 is the output of the interpolation circuit.

The outputs of the latch circuits 41 and 42 correspond to a and a in FIG. 6, respectively. The output of the eye circuit 43 is (ba) in equation (1). Furthermore, the output (b-IL) by the combination of the adder circuit 44 and the latch 46 is
! Ru. Refaresis clock l<The frequency of the output of the pulse generation circuit 46 is S aZ , and the frequency of the output of the manual clock generator 23 is 10KH2, so the counter 4
The output of 7 becomes SOO.

At this time, 1o6/1soo=174s is output as the output of the slope coefficient generating circuit 48, which is configured in a ROM, for example. That is, if the counter is 4, □ is set to k. As a result, the output of the multiplier circuit 49 is (
b-1)·n-1 is obtained. Furthermore, as the output of the adder circuit 6o, a + (' b -IL)・n- of equation (1)
k is obtained. Therefore, the output 66 of the interpolation circuit and the dotted line 32 in FIG. 6 are obtained. Here 1 and b
The polarity bit changes depending on the magnitude relationship. In Fig. 7, the second term of equation (1) is configured to calculate (ba-a)xn first, but depending on the hardware, it may overflow at this stage.
If the configuration is such that kXn is calculated first, there will be no such fear.

In the above manner, the output of the interpolation circuit 16 shown in FIG. 3 is obtained.
The sound is reproduced at a variable speed through a speaker 21 via a %D/mu converter 18, a low-pass filter 19, and an amplifier 2o, and the sound can be monitored. At this time, if the rotary dial is rotated in the forward and reverse directions, the user can hear exactly the same reproduction sound as when the 17-A/ of a conventional analog tape recorder is manually rotated in the forward and reverse directions.

In this way, stop the rotary dial at the point you want to edit, and send a signal to CjPU5 that that point is the editing point.This means that the position of the starting point 4 of MU in Figure 2 has been externally determined. In order for the CPU 6 to recognize this position, it goes through the following process.First, at the editing point given by the editor, the code input signal input at the same time as the PGM data is time coated. CPU 5 via interface 26 and path line 8
reads and saves to %PAM7. Here SMPTIC
In timecode, the minimum signal unit is a frame (1/30th of a second), so in order to increase the editing accuracy beyond this, the audio sampling pulses must be counted within the frame and the number of samples within the frame must be calculated. It is also necessary to read the information on whether the CPU has the data and save it in the PAM 7, but the counter is omitted and it is included in the time code interface circuit 26. Therefore, at this point, cptrs is the gin, minute, and second information.・Reading the frame sample information results in .Next, in the edit point search mode, the address counter 13 and the time code interface 2 are read by the output of the manual clock pass generator 23.
The counter in 6 operates, and the CPU 5 reads the time code information and the sample point information in the finer frame unit, that is, the hour, minute, second, frame, and sample information of the correct edit point that has been manually corrected. (not shown).

Let this information be SPl. In this way, the CPU 5 has information on the exact position of the sample point in the memory 12 and on the tape.

Next, as shown in FIG. 2 (determine the boundaries of the first tape 1 and B of sLl), in the same manner as described above, the editor wants to edit while monitoring the output audio from the speaker 21, that is, the first tape A signal to that effect is input from the operation input unit 9 in the same way as described above near the boundary of B and B. After that, writing continues in the memory 12 for a certain period of time, and the process is the same until it stops. However, in this case Assuming that the capacity of the memory 12 is approximately 6 seconds, the memory 1
Stop writing to 2. The state of memory 12 at this time is shown in Figure 8, and X and Y are "P'l," respectively.
Corresponds to 'yP'. The operation of searching for the correct editing point in the memory 12 is the same as described above, and the switches a and b are turned on in the switch 11.
, +1-f of the switch 24 is turned on.

When the rotary dial is rotated in the forward direction, the contents of the memory 12 are played back in the order of XP1 → YP1, and when it is rotated in the reverse direction, the contents of the memory 12 are played back in the order of X, 1-+0OOOO → 2FFFF → ("
p1+1). In this way, the audio is played back as the rotary dial rotates, so it is possible to stop the rotary dial at the correct position and designate this point as an editing point. The position information of this point is read into the CPU 5 and stored in the RAM 7 by the same operation as in the case described above.

The memory address of this point is Xp-++Np+ f
Ru.

Also, as described above, the time code information and sample point information of the manually corrected accurate editing point are assumed to be lEp+.

Next, the edit point set above (address xP in memory)
1+NPI) is correct or not, the contents of the memory 12 are read out continuously at the specified address using the reference clock, and the editor uses the operation input section 9 to switch the device into edit point memory/pre-monitor mode. Will it happen? By keeping it constant, control of each part is as follows. The switch 17 has a-c set to 0)11. , the switches a to e of the switches 24 are turned on. The enemy 6ptrs stores address 1 and counter information yp1 stored in RAMy,
The address counter 13 is preset as an initial value via the interface element 14. This value is also input to the address detector 27 and IPI + 1
ipt is calculated and held. Reference clock generation circuit 2
The clock signal generated from 2 is passed through switch 24,
Input to address counter 13. address counter 1
? is the instruction of CPU5 (based on Yp, -+2 F F
F F-+0OOOO-+XpI+Npt (At the same time as changing the address in the order of D and reading out the memory 12,
This address is transferred via interface element 14 to C
The data is input to the PU 5, sequentially stored in the RAM 7, and simultaneously input to the address detector 27. The digital signal read out from the frame 12 passes through the interpolation circuit 16, and is then transferred to the switch 17, the D/mu converter 18, and the low-pass filter 1.
9. The signal is monitored as a continuous audio signal from the speaker 21 via the amplifier 2o. Then, the address detector 27 detects that the content of the address counter 13 is the edit point (
XPl + NPl), ■ Turn on the lamp 28 on the control output part q via Denita Vanu 8 and interface element 7710, ■ Change the monitor and loudspeakers, ■ Install a monitor speaker of 21- or more, and edit this. Notify the editor of the editing point by switching the speakers at the point or outputting an oscillating sound. Note that the address of the edit point is also held in the RAM 7. If there is a problem with the edit point in the edit point memory/pre-monitor mode described above, the process from the process of determining the edit point in memory is repeated, and if a suitable edit point is obtained, the process proceeds to the next step.

Next, the second tape 2 shown in FIG. 2(b) is 0. In order to determine the Df4 field, part 2 of the second tape is played back by the playback tape recorder M and inputted to the P2 terminal. At this time, the g-i of the switch 118 is ON, and when PCM data is input to the h terminal, this data is transferred to the switch 1.
1, the data is cyclically recorded in the memory 12.

□From now on, start point 4 of the first tape shown in Figure 2 (a)
Since the content is the same as that for determining , the explanation will be omitted. Let X and Y in FIG. 4 set here be 6 x P2 * "P2," and let the address in the memory 12 at the editing point be "xP2 + NP2," the time code information, and the sample point information as "P2."

Next, the edit point set above (address XP in memory)
2+NP2) is correct or not, the contents of the memory 12 are continuously read and monitored for the specified addresses using the reference clock, but the editor enters the editing point memory/pre-monitor mode from the operation input section 9. With these settings, each part will be controlled as follows.

As for the switch 17, a-c are ON l, 1. , y, switch 24 turns on d-e. In addition, CPU5 is RAM7
Address counter information Yp2+1 stored in data bus 8. The address counter 13 is preset as an initial value via the interface element 14.

At the same time, this value is input to the address detector 27 and the editing point is preset. A clock signal generated by the reference clock generation circuit 22 is input to the address counter 13 via the switch 24. The address counter 13 is cp
Based on vs instruction Ypz +1-+2 F F F
At the same time as F-+0OOOO→Xp2+Np2, this address is transferred to 0-P via the interface element 14.
The data is input to U5, sequentially held in RAM7, and is also input to address detector 27. The digital signal read out from the memory 12 passes through the interpolation circuit 16, and then passes through the switch 17 and the D/D converter 18. The signal passes through a low-pass filter 19 and an amplifier 2o and is monitored as a continuous audio signal from a speaker 21. Then, the address detector 27 detects that the content of the address counter 13 is the edit point (xP2) on the boundary between O and D.
+”P2) IICfx root, 7' -p /<
control output section q via interface element 10
The editor is notified of the edit point by the same means as for the edit point described above, such as lighting the lamp 28, changing the monitor level, or outputting an oscillating sound. The edit point of st is also held in the RAM 7. If there is a problem with the edit point in the above edit point memory/pre-monitor mode, repeat the process starting from the process of determining the edit point in memory.
After appropriate editing, as shown in the third tape in Figure 2 (C),
and D from the operation input section 9. For example, this is 0.1
g.

By selecting one of the operation buttons such as 0.3B, 0.68.1B, 28,411.88, etc., the sandstone is turned. Then, run the playback tape recorders L and M to check whether the editing time, B, C, D or cross-fade time is edited to suit the purpose without recording it on the actual tape. Perform the action. At this time, the purpose is to monitor the connection of audio signals before and after the editing point, and by setting the device to the tape pre-monitor mode from the operation input section 9, the editor can
From PU5! Rewind the time necessary for the playback side tape recorder (for example, L2 in Figure 2) for the time required for the playback side tape recorder to control the synchronous travel, and set the playback state so that each edit point KPI and xP2 found above are the same time. Figure 3 P
Each tape is synchronously controlled so that 1 and negative inputs are input, and the timing is adjusted by an appropriate delay circuit.

First, only the signal shown in FIG. 2(a) is passed through the cross-fade processing circuit 16. Next, when the editing point "PI" of the first tape in FIG. Cross-fade with the digital signal of the second tape D in FIG. 2(b). Here, the above-mentioned cross-fade processing will be specifically described. FIG. 9 shows the cross-fade processing circuit 1 in FIG. 3.
FIG. 6 is a detailed block diagram of FIG.

Fil is an input from h in FIG. 3, and Fi2 is also an input from negative. OK is the sampling clock pass input. 61 is a fade curve generation circuit that digitally generates coefficients of a cross-fade curve;
It is composed of a counter or a combination of an address counter and a ROM. An example of the output of this circuit 61 is shown at 66 in FIG. Here, the vertical axis is 0 obtained by D/mu conversion of the above coefficients.The output of the need curve generation circuit 61 is digitally multiplied by the POM audio signal input from Fil.

As a result, the output of the multiplication circuit 62 fades out the input from Fil and becomes a normal output. 63 is a fade curve generating circuit similar to 61, and an example of its output is shown in 67 in FIG.
Shown below. 64 is a multiplication circuit that multiplies the input of Fi20 and the output of 63, and the output of the multiplication circuit 64 fades in the input from Fi2. 66 is a multiplication circuit 64
This is an adder circuit that adds the outputs of and 62, and the output of and 10
is digitally crossfated: and the original signal is obtained.

In this way, a signal cross-faded at the editing point is obtained at the output of the fade processing circuit 16.

Next, when the crossfade time ends, the cross ta,i
:::The m path outputs only the signal input from P2 to the digital signal output of the cross-fade processing circuit 16, and outputs the digital signal from the switch 17. D/mu converter 18, low-pass filter 19
, amplifier 20. Monitoring is performed via the speaker 21. At this time, switches 17゜24 are of course a-b and d-e turned on.
It is.

As mentioned above, the exact editing point on the tape is stored in RAM 7, so the synchronized running of the tape, the delay amount of the delay circuit mentioned above, the cross-fade timing, etc. are all controlled by the CPU.
This is done by command from 5.

Through the above process, the tape pre-monitoring is completed, and if there is a problem with the connection of sounds near the editing point, the editing point determination process is repeated, and if a suitable editing point is obtained, the next editing process is started.゛In editing work, the operation near each editing point is the same as that of the tape pre-monitor, but in editing work, the necessary parts of the first and second tapes in Figure 2 are played back and the third tape is played back. Since it is necessary to record on the tape of
) rewind to just before the start of the first tape. In addition, the tape recorder certificate on the playback side is shown in Figure 2 (b).
Edit point C and D of the tape EP2 Rewind the original time. Then, the playback side tape recorder L plays back the tape, passes through the cross fade processing circuit 16 shown in FIG. 2 (al) to the P1 terminal shown in FIG. A recorder is connected and this tape recorder is put into a recording state.

Next, when the playback side tape recorder L plays back up to 51 points before the crossfade part in Figure 2 (No. Synchronize and control each tape so that it is input to P1 and h in Figure 3 at the same time, and adjust the timing using an appropriate delay circuit.After that, perform exactly the same operation as the second tape pre-monitor operation. As a result, the data is edited in the recording side tape recorder connected to the R terminal as shown in FIG. 2 (0).

According to the above embodiment, since editing is done at the stage of the audio PCM signal itself, regardless of the recording format of the tape deck, the problem occurs during manual editing 3 when newly reorganized and recorded on the recording side tape recorder. There will be no loss of information.

Therefore, it is extremely important to correctly detect and determine the edit point, but in the above-mentioned θ embodiment, when reading out and monitoring the memory 12, when a specific address recorded in the address detector 27 as an edit point is reached, Since the editor is notified by lighting of the lamp 28, change in monitor status, alarm sound, etc., it is immediately possible to determine whether or not the above-mentioned editing point was appropriate during monitor playback. If the editing point is inappropriate, it can be converted very easily by simply rewriting it in the memory, and it is possible to immediately reproduce it in the memory and confirm it by notification.

Furthermore, in the above configuration, when playing back from the memory 12,
Even when driven at a variable speed, interpolation does not adversely affect the reproduced signal, so editing points etc. can be easily selected by manually reproducing at a slow speed or reproducing in the opposite direction. Further ゛−
Since the fish gathering position information is provided by using a time code and a sampling pulse in combination, the positional accuracy can be improved to the accuracy of the sampling pulse. Therefore, when performing cross-fade processing, editing points can be easily and accurately determined.
It is possible to eliminate unnatural editing conditions caused by signal loss or discontinuity.

In the above embodiment, the address detector 7 which stores a specific address and outputs a signal indicating the match with the evening output using the address color is taken out and shown.
tq22::. :;fu τ: τ not there.

As described above, according to the present invention, the reproduced signal is stored in the first memory, the address (specific address) for the desired point is stored in the second memory, and the reproduced signal is stored in the first memory.
If the specific address is detected when the specific address is read out from the memory and monitored, the editor is notified, so that the editor can accurately know the points that should be used as various standards such as editing points. Therefore, it is possible to prevent inadvertent omissions and discontinuities in the digital signal, and it is possible to accurately mark editing points, etc., especially when editing digitally recorded tapes by performing cross-fade processing. Even in cases where it is necessary to define a value, it has the excellent effect of allowing editing work to be performed easily and with high precision.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing the concept of analog editing, FIG. 2 is an explanatory diagram showing the concept of the editing method adopted in the digital signal editing device of the present invention, and FIG. 3 is an implementation of the digital signal editing device of the present invention. A block diagram showing an example, FIG. 4 is an explanatory diagram showing the write state of the memory, FIG. 6 is a waveform diagram explaining the concept of interpolation, FIG. 6 is a waveform diagram explaining the interpolation function of this embodiment, and FIG. The figure is a proref diagram showing the configuration of the interpolation circuit, Figure 8 is an explanatory diagram showing the memory write state, Figure 9 is a block diagram showing the configuration of the cross-fade processing circuit, and Figure 10 is the output of the fade curve generation circuit. It is a characteristic diagram shown after D/mu conversion. 6...cpu, e...ROM,?・・・
...RAM. 9...Operation input section, q...Control output section, 12...Memory, 13...Address counter, 16...Cross fade processing circuit,
16...Interpolation circuit, 18 paths, 23...Manual clock pulse generator, 27...Name of agent Patent attorney Toshio Nakao 1 person Figure 4 Figure 5 [8 Figure i! 'l 'l 'l, 11 seconds AL Figure 9 Figure 10

Claims (1)

[Claims] a first memory that stores the reproduced digital signal;
clock pulse generation means for writing a digital signal into the first memory or reading a signal from the first memory via an address setting means; 2, a means for converting the digital signal read from the first memory into an analog signal; and a means for monitoring the address setting means while reading the digital signal from the first memory, What is claimed is: 1. A digital signal editing device comprising means for detecting and notifying.