JPS5851333U - Program processing device - Google Patents
Program processing deviceInfo
- Publication number
- JPS5851333U JPS5851333U JP14656181U JP14656181U JPS5851333U JP S5851333 U JPS5851333 U JP S5851333U JP 14656181 U JP14656181 U JP 14656181U JP 14656181 U JP14656181 U JP 14656181U JP S5851333 U JPS5851333 U JP S5851333U
- Authority
- JP
- Japan
- Prior art keywords
- processing device
- program processing
- central control
- flip
- keyboard
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Calculators And Similar Devices (AREA)
- Debugging And Monitoring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来の装置のブロック図、第2図はその流れ図
、第3図は本考案実施例のブプログラム処理装置のブロ
ック図、第4図は第3図の装置の流れ図である。
1・・・・・・中央制御装置(CPU)、3・・曲読出
専用メモリ、4・・・・・・書込読出メモリ、5・・曲
キーボード、6・・・・・・入出力ポート、7・・・・
・・アドレス・データバス、8・・・・・・コントロー
ルバス、9・・・・・・フリップフロップ。FIG. 1 is a block diagram of a conventional apparatus, FIG. 2 is a flowchart thereof, FIG. 3 is a block diagram of a program processing apparatus according to an embodiment of the present invention, and FIG. 4 is a flowchart of the apparatus shown in FIG. 1... Central control unit (CPU), 3... Song read-only memory, 4... Write/read memory, 5... Song keyboard, 6... Input/output port ,7...
...Address/data bus, 8...Control bus, 9...Flip-flop.
Claims (1)
憶回路と、キーボードと、前記中央制御装置からの制御
信号でセットされ少なくとも前記キーボードからの制御
信号でリセットされるフリップフロップとを備え、前記
フリップフロップの出力信号で前記中央制御装置の内部
の状態は保持したまま機能を停止させる事を特徴とする
プログラム処理装置。a central control unit for processing microprogramming, a memory circuit, a keyboard, and a flip-flop set by a control signal from the central control unit and reset by at least a control signal from the keyboard; an output of the flip-flop; A program processing device characterized in that a signal causes the central control device to stop functioning while maintaining its internal state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14656181U JPS5851333U (en) | 1981-09-30 | 1981-09-30 | Program processing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14656181U JPS5851333U (en) | 1981-09-30 | 1981-09-30 | Program processing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5851333U true JPS5851333U (en) | 1983-04-07 |
Family
ID=29939466
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14656181U Pending JPS5851333U (en) | 1981-09-30 | 1981-09-30 | Program processing device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5851333U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61123169U (en) * | 1985-01-18 | 1986-08-02 | ||
| JPS61137759U (en) * | 1985-02-18 | 1986-08-27 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4842364A (en) * | 1971-09-30 | 1973-06-20 | ||
| JPS52149432A (en) * | 1976-06-08 | 1977-12-12 | Toshiba Corp | Electronic device |
-
1981
- 1981-09-30 JP JP14656181U patent/JPS5851333U/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4842364A (en) * | 1971-09-30 | 1973-06-20 | ||
| JPS52149432A (en) * | 1976-06-08 | 1977-12-12 | Toshiba Corp | Electronic device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61123169U (en) * | 1985-01-18 | 1986-08-02 | ||
| JPS61137759U (en) * | 1985-02-18 | 1986-08-27 |
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