JPS5851602A - Orthogonal modulation circuit - Google Patents
Orthogonal modulation circuitInfo
- Publication number
- JPS5851602A JPS5851602A JP56149996A JP14999681A JPS5851602A JP S5851602 A JPS5851602 A JP S5851602A JP 56149996 A JP56149996 A JP 56149996A JP 14999681 A JP14999681 A JP 14999681A JP S5851602 A JPS5851602 A JP S5851602A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- orthogonal modulation
- phase shifter
- circuit
- orthogonality
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03C—MODULATION
- H03C1/00—Amplitude modulation
Landscapes
- Amplitude Modulation (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は90移相器に生ずる誤差を相殺して直交度を維
持し得る直交変調回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a quadrature modulation circuit capable of canceling errors occurring in a 90 phase shifter and maintaining orthogonality.
従来の直交変調回路は第1図のように構成されている。A conventional quadrature modulation circuit is configured as shown in FIG.
直交変調された信号成分間の直交度に誤差が生じて来る
場合には9C移相器+1)を調整して直交度を維持する
手段が採られている。When an error occurs in the degree of orthogonality between orthogonally modulated signal components, a means is adopted to maintain the degree of orthogonality by adjusting the 9C phase shifter +1).
陶、第1図において、(2)、(3)はミクサー(平衡
変調器)、(菊はハイブリット回路である。In Figure 1, (2) and (3) are mixers (balanced modulators), and the chrysanthemum (chrysanthemum) is a hybrid circuit.
上記手段による直交度の調整には、9C移相器の製造上
の理由、例えに変調回路のモジュール化、量産化等によ
りその調整が困難乃至不能となる。このことF1a然の
仁となから、直交変調信号の直交度を9Cに保ち得なく
なり、所望の直交変調信号を送信出来ないことになる。Adjustment of orthogonality using the above means is difficult or impossible due to manufacturing reasons for the 9C phase shifter, such as modularization and mass production of modulation circuits. Due to this fact, the degree of orthogonality of the orthogonal modulation signal cannot be maintained at 9C, and the desired orthogonal modulation signal cannot be transmitted.
本発明は土浦し九ような従来回路の有する欠点を解決す
べく創案されたもので、その目的は被変調信号の直交変
調に先立ってその信号に相殺成分を生じさせて直交変調
で生ずる誤差分を零にするようにして直交変調信号の直
交度を9σ移相器で生ずる誤差分に無関係に維持し得る
直交変調回路を提供することにある。The present invention was devised to solve the drawbacks of conventional circuits such as Shiku Tsuchiura's.The purpose of the present invention is to generate a cancellation component in the modulated signal prior to orthogonal modulation of the signal to compensate for the error caused by the orthogonal modulation. An object of the present invention is to provide an orthogonal modulation circuit that can maintain the orthogonality of an orthogonal modulation signal by making it zero irrespective of the error generated in a 9σ phase shifter.
以下、添付図面を参照しながら本発明の一実施例を説明
する。Hereinafter, one embodiment of the present invention will be described with reference to the accompanying drawings.
第2図は本発明の実施例回路を示す。この回路■は直交
変調されるべき一方の被変調信号例えばY信号を係数器
α)を介して加算回路体)の−方の入力へ供給すると共
に加算回路(8)の他方の入力へ他方の被変調信号、例
えばX信号を供給して合成し、その合成信号と上記一方
の被変調信号とを第1図の直交変調回路(2)のそれぞ
れの入力へ供給するように構成されている。この回路(
圀において、係数器はY信号への重み付けを調整しうる
重み調整可能な係数器として構成されるのがよい。FIG. 2 shows an embodiment circuit of the present invention. This circuit (2) supplies one modulated signal to be orthogonally modulated, such as a Y signal, to the - input of the adder circuit (8) via the coefficient unit α), and also supplies the other input of the adder circuit (8) to the - input of the adder circuit (8). The modulated signal, for example, the X signal, is supplied and combined, and the combined signal and the one modulated signal are supplied to respective inputs of the orthogonal modulation circuit (2) in FIG. This circuit (
In the field, the coefficient multiplier is preferably constructed as a weight-adjustable coefficient multiplier that can adjust the weighting applied to the Y signal.
次に1上記構成の本発明回路の動作を説明する。Next, the operation of the circuit of the present invention having the above configuration will be explained.
第2図回路の9σ移相器+1)に誤差が々く、従って係
数器(7)の出力も零に調整された状態においては、被
変調信号(X)、(Y)は第1図に示される従来の直交
変調回路(6)で直交変調されたと同様となり、ハイブ
リット回路(4)の出力、即ち直交変調回路人は
コニ
A = X + Y6 2で表わされ
る如くなり、直交度は9ぴに保たれている。When the 9σ phase shifter (+1) in the circuit in Figure 2 has a large error and the output of the coefficient multiplier (7) is also adjusted to zero, the modulated signals (X) and (Y) are as shown in Figure 1. The output of the hybrid circuit (4), that is, the output of the orthogonal modulation circuit is expressed as A = X + Y6 2, and the degree of orthogonality is 9 perfect. is maintained.
とのような直交変調を生じさせている変調回路の9C移
相器(1)にδだけの誤差が生じるに至り九とすると、
直交変調信号Aは
A = X + Yej(2+δ)で表わされ
る信号となり、直交変調信号の直交度がδだけずれて来
る。Assuming that an error of δ occurs in the 9C phase shifter (1) of the modulation circuit that produces orthogonal modulation as shown in 9,
The orthogonal modulation signal A becomes a signal expressed by A = X + Yej (2+δ), and the orthogonality of the orthogonal modulation signal shifts by δ.
この時、係数器蒐ηの信号(Y)への重み付与量をxi
sδになるように調整すると、その時の直交変調信号A
は
A = X + Ys(sδ十 Yej(−;
−M)= X + Yjcoaδ
となる、つまり、この直交変調信号の直交度は9fに維
持される。At this time, the weighting amount of the coefficient unit η to the signal (Y) is set as xi
When adjusted so that sδ becomes sδ, the orthogonal modulation signal A at that time
is A = X + Ys(sδ ten Yej(-;
−M)=X+Yjcoaδ, that is, the orthogonality of this orthogonal modulation signal is maintained at 9f.
このように、本発明による直交度の維持は9σ移相器を
少しも調整することなく達成される。Thus, maintaining orthogonality according to the present invention is achieved without any adjustment of the 9σ phase shifter.
従って、9f移相器に全く調整機能を有しなくとも、或
いはその調整機能による調整が困難乃至不能になる環境
に置かれたとしても、直交変調信号の直交度を所望の値
に維持し得る。Therefore, even if the 9f phase shifter has no adjustment function at all, or even if it is placed in an environment where adjustment using the adjustment function is difficult or impossible, the orthogonality of the orthogonal modulation signal can be maintained at a desired value. .
上記実施例においては、2つの被変調信号について述べ
たが、相互に直交変調される3以上の被変調信号に対し
ても本発明を適用しうるものである。In the above embodiment, two modulated signals have been described, but the present invention can also be applied to three or more modulated signals that are mutually orthogonally modulated.
以上要するに、本発明によれば、9C移相器を伺んら調
整することなく直交変調信号の直交度を所望の値に維持
し得る。このことは直交変調器のモジュール化、集積回
路化に伴って9σ移相器での調整に依存し得なくなる場
合に、特にその有用性を発揮する。In summary, according to the present invention, the degree of orthogonality of the orthogonal modulation signal can be maintained at a desired value without making any adjustments to the 9C phase shifter. This is especially useful when quadrature modulators become modular and integrated circuits and can no longer rely on adjustment by a 9σ phase shifter.
第1図は公知の直交変調回路図、第2図は本発明の直交
変調回路図である。
図中、(1)は9σ移相器、(2)、 (3)鉱ミクサ
ー、(4はハイブリット回路、ff)は係数器、(8)
は加算回路である。
第1図
第2図FIG. 1 is a diagram of a known quadrature modulation circuit, and FIG. 2 is a diagram of a quadrature modulation circuit according to the present invention. In the figure, (1) is a 9σ phase shifter, (2), (3) is a mixer, (4 is a hybrid circuit, ff) is a coefficient unit, (8)
is an adder circuit. Figure 1 Figure 2
Claims (2)
器を介して加算回路へ供給して他方の被変調信号と合成
し、その合成信号と上記一方の被変調信号とを直交変調
するように構成したことを特徴とする直交変調回路。(1) One modulated signal whose orthogonality I4 should be decreased is supplied to an adder circuit via a coefficient unit and combined with the other modulated signal, and the combined signal and the above-mentioned one modulated signal are orthogonally modulated. A quadrature modulation circuit characterized by being configured as follows.
とを特徴とする特許請求の範囲第1項記載の直交変調回
路。(2) The orthogonal modulation circuit according to claim 1, wherein the coefficient unit is constructed as a weight-adjustable coefficient unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56149996A JPS5851602A (en) | 1981-09-22 | 1981-09-22 | Orthogonal modulation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56149996A JPS5851602A (en) | 1981-09-22 | 1981-09-22 | Orthogonal modulation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5851602A true JPS5851602A (en) | 1983-03-26 |
| JPH0350445B2 JPH0350445B2 (en) | 1991-08-01 |
Family
ID=15487180
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56149996A Granted JPS5851602A (en) | 1981-09-22 | 1981-09-22 | Orthogonal modulation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5851602A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60145754A (en) * | 1984-01-09 | 1985-08-01 | Nec Corp | Quadruple phase modulator |
| JPH02211748A (en) * | 1989-02-10 | 1990-08-23 | Nec Eng Ltd | Orthogonal modulation circuit |
-
1981
- 1981-09-22 JP JP56149996A patent/JPS5851602A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60145754A (en) * | 1984-01-09 | 1985-08-01 | Nec Corp | Quadruple phase modulator |
| JPH02211748A (en) * | 1989-02-10 | 1990-08-23 | Nec Eng Ltd | Orthogonal modulation circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0350445B2 (en) | 1991-08-01 |
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