JPS5856529A - Semiconductor solid-state relay - Google Patents

Semiconductor solid-state relay

Info

Publication number
JPS5856529A
JPS5856529A JP15378181A JP15378181A JPS5856529A JP S5856529 A JPS5856529 A JP S5856529A JP 15378181 A JP15378181 A JP 15378181A JP 15378181 A JP15378181 A JP 15378181A JP S5856529 A JPS5856529 A JP S5856529A
Authority
JP
Japan
Prior art keywords
power supply
scr2
gate
full
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15378181A
Other languages
Japanese (ja)
Inventor
Hirotoshi Toida
裕俊 戸井田
Toshiaki Hagiwara
利明 萩原
Kazuo Tominaga
富永 和雄
Yasuhiro Masuko
益子 康弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Industry and Control Solutions Co Ltd
Original Assignee
Hitachi Engineering Co Ltd Ibaraki
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Engineering Co Ltd Ibaraki, Hitachi Ltd filed Critical Hitachi Engineering Co Ltd Ibaraki
Priority to JP15378181A priority Critical patent/JPS5856529A/en
Publication of JPS5856529A publication Critical patent/JPS5856529A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/13Modifications for switching at zero crossing

Landscapes

  • Electronic Switches (AREA)

Abstract

PURPOSE:To obtain a large output, using a semiconductor control rectifier of a small capacity, through the connection of an input terminal of a full-wave rectifier circuit to one terminal of an AC power supply and a plurality of semiconductor controlling rectifiers connected to the AC power supply. CONSTITUTION:When an input signal is applied to terminals 9 and 10, a photothyristor SCR2 receives a light trigger signal of a light emitting diode 3 but since a transistor TR12 turns on with a high power supply voltage and the gate and cathode of the SCR is short-circuited, the SCR2 is not turned on. When the power supply voltage comes close to zero volt, the TR12 is turned off, the SCR2 is triggered and pulsive currents are applied to the gate of Triacs TAC19, 20 via a full-wave rectifier circuit 1 to trigger both the TACs. When the polarity of the power supply voltage is changed, the TR12 is turned off until the base potential of the TR12 reaches a constant value and a current flows to the gate of the TAC19, 20, the circuit 1 and the SCR2 and the TAC19, 20 remained being triggered and an AC load current flows. Through the use of a plurality of TACs, the load current of large capacity can be controlled.

Description

【発明の詳細な説明】 本発明は半導体固体リレーに係り、小容量の半導体制御
整流装置を用いて大容量出力を得ることができる半導体
固体リレーを提供することを目的としており、その特徴
とするところは、全波整流回路の出力端子間に第1の半
導体制御整流装置が接続され、この半導体制御整流装置
には点弧手段と全波整流回路出力電圧がほぼ零になる時
にその制御端子と一生端子間の短絡を解く短絡手段を有
し、全波整流回路の一入力端子は交流電源の一端に接続
され、他の入力端子は交流電源に接続された複数個の第
2の半導体制御整流装置の各制御端子と接続されている
ことにある。
[Detailed Description of the Invention] The present invention relates to a semiconductor solid state relay, and an object of the present invention is to provide a semiconductor solid state relay that can obtain a large capacity output using a small capacity semiconductor controlled rectifier. However, a first semiconductor-controlled rectifier is connected between the output terminals of the full-wave rectifier, and this semiconductor-controlled rectifier has an ignition means and a control terminal that connects the full-wave rectifier when the output voltage of the full-wave rectifier becomes approximately zero. The full-wave rectifier circuit has short-circuiting means for breaking short-circuits between the terminals, one input terminal of the full-wave rectifier circuit is connected to one end of the AC power supply, and the other input terminal is connected to a plurality of second semiconductor-controlled rectifiers connected to the AC power supply. It is connected to each control terminal of the device.

以下、図面に示す一実施例により本発明を説明する。The present invention will be explained below with reference to an embodiment shown in the drawings.

第1図にお℃て、1は全波整流回路で出力端子間にホト
サイリスタ2が接続されている。ホトサイリスタ2は発
光ダイオード3とホトカッブリングしており1発光ダイ
オード3は抵抗4,5、トランジスタ6.7からなる定
電流回路、ダイオード8を介して直流信号入力端子9,
10に接続されている。ホトサイリスタ2のゲート・カ
ソード端子間には抵抗11.トランジスタ12が接続さ
れ、トランジスタ12は、全波整流回路1の出力端子間
に設けられた分圧抵抗13,14,15そしてコンデン
サ16によって駆動される。全波整流回路1の一入力端
子は交流電源の一端子17と接続され、残シの入力端子
は交流電源端子17゜18間に設けられた2個のトライ
アック19゜20のゲート端子と接続されている。抵抗
21、コンデンサ22はトライアック1.9,20のス
ナバ−回路を構成している。負荷は図示されていないが
、交流電源端子17.18と交流電源の間に設けられて
いる。
In FIG. 1, reference numeral 1 denotes a full-wave rectifier circuit, and a photothyristor 2 is connected between its output terminals. The photothyristor 2 is photocoupled with a light emitting diode 3, and the light emitting diode 3 is connected to a constant current circuit consisting of resistors 4 and 5 and a transistor 6.7, and a DC signal input terminal 9 through a diode 8.
10. A resistor 11 is connected between the gate and cathode terminals of the photothyristor 2. A transistor 12 is connected and is driven by voltage dividing resistors 13, 14, 15 and a capacitor 16 provided between the output terminals of the full-wave rectifier circuit 1. One input terminal of the full-wave rectifier circuit 1 is connected to one terminal 17 of the AC power supply, and the remaining input terminals are connected to the gate terminals of two triacs 19.20 provided between the AC power supply terminals 17.18. ing. A resistor 21 and a capacitor 22 constitute a snubber circuit for triacs 1.9 and 20. Although the load is not shown, it is provided between the AC power supply terminals 17 and 18 and the AC power supply.

図示する半導体固体リレーの動作を第2図に示す波形と
共に簡単に説明する。
The operation of the illustrated solid-state semiconductor relay will be briefly explained together with the waveforms shown in FIG.

第2図(a)に示すように入力端子9,10に入力信号
が印加されない状態では端子17.18に第2図(b)
K示す電源電圧が加えられてもホトサイリスク2は点弧
せず、従って全波整流回路1を介してトライアック19
,20には点弧信号は印加されず、トライアック19,
20はオフ状態を保ち、負荷電流は流れない。
As shown in Fig. 2(a), when no input signal is applied to input terminals 9 and 10, terminals 17 and 18 are connected to terminals 17 and 18 as shown in Fig. 2(b).
Even if a power supply voltage indicated by
, 20, no firing signal is applied to the triacs 19, 20,
20 remains off and no load current flows.

入力信号が加えられると、ホトサイリスタ2は発光ダイ
オード3の光点弧信号を受けるが、電源電圧が高い状態
ではトランジスタ12がオン状態にあってゲート・カソ
ード端子間を短絡しているので1点弧しない。電源電圧
が低下して零ボルト近くになると、トランジスタ12の
ぺ〜スミ位も低下し、オフ状態となってホトサイリスタ
2のゲート・カソード端子間の短絡を解放する。このた
め、ホトサイリスク2は点弧して、全波整流回路1を介
しての脈流がトライアック19.20のゲート端子に加
わり、両トライアック19.20が点弧する。電源電圧
の極性が変った場合1 トランジスタ120ベース電位
が一定値rなるまでは。
When an input signal is applied, the photothyristor 2 receives a light ignition signal from the light emitting diode 3, but when the power supply voltage is high, the transistor 12 is in the on state and the gate and cathode terminals are short-circuited, so there is only one point. No arc. When the power supply voltage decreases to near zero volts, the voltage level of the transistor 12 also decreases, turning off the transistor 12 and releasing the short circuit between the gate and cathode terminals of the photothyristor 2. For this reason, the photothylisk 2 is ignited, the pulsating current through the full-wave rectifier circuit 1 is applied to the gate terminal of the triac 19.20, and both triacs 19.20 are ignited. When the polarity of the power supply voltage changes 1 Until the base potential of the transistor 120 reaches a constant value r.

トランジスタ12はオフ状態であり、この間にトライア
ック19,20のゲート端子、全波整流回路1、ホトサ
イリスク2を介して電流が流れるため、トライアック1
9.20は点弧する。つまI)、入力端子9,10に点
弧信号が加えられている状態ではl・ライアツク19.
20は点弧しつづけ、第2図(C)に示すように交流の
負荷電流が流れる。
The transistor 12 is in an off state, and during this time current flows through the gate terminals of the triacs 19 and 20, the full-wave rectifier circuit 1, and the photothyrist 2, so that the triac 1
9.20 fires. 1), when the ignition signal is applied to the input terminals 9 and 10, the ignition signal 19.
20 continues to fire, and an alternating current load current flows as shown in FIG. 2(C).

入力端子9,10から点弧信号が加わらなくなると、負
荷電流は、半波周期分だけ流れた後、ホトサイリスタ2
、トライアック19,20がオフ状態を保つために流れ
なくなる。即ち、この半導体固体リレーは入力信号のオ
ン・オフに従って電源電圧が零ボルト近くになるのを待
って、負荷電流が流れおり、シゃ断されたシするもので
ある。
When the ignition signal is no longer applied from the input terminals 9 and 10, the load current flows for a half-wave period, and then the photothyristor 2
, the triacs 19 and 20 remain off, so that no current flows. That is, this solid-state semiconductor relay waits until the power supply voltage becomes close to zero volts as the input signal turns on and off, and then the load current stops flowing and is cut off.

このような半導体固体リレーにおける容量は負荷電流を
制御するトライアック19.20の容量によって決まる
The capacity in such a semiconductor solid state relay is determined by the capacity of the triac 19,20 that controls the load current.

本発明では、トライアック19,20の2 iti!i
lを用い、共通のゲート点弧信号で制御している。これ
は、従来、負荷電流の大容量化に伴って大容量の1個の
トライアックを用いていたものに対し、小容量の2個の
トライアックを用いることにより、トライアックの入手
を容易にして、容易に半導体固体リレーを得ようと云う
ものである。大容量のトライアックの入手は困難で、大
容量化するほど困難度は増加する。本発明では複数のト
ライアックを並列接続しているので、入手に困難さはな
い。
In the present invention, 2 iti! of triac 19, 20! i
1 and controlled by a common gate firing signal. This has made it easier to obtain triacs by using two small-capacity triacs instead of the conventional single large-capacity triac that was used to accommodate larger load currents. The aim is to obtain a semiconductor solid-state relay. It is difficult to obtain a large-capacity triac, and the difficulty increases as the capacity increases. In the present invention, since a plurality of triacs are connected in parallel, there is no difficulty in obtaining them.

!、た、同一ゲート点弧信号を用いているので、トライ
アックの特性さえ一致していれば、一部のトライアック
に負荷電流が集中することもない。トライブックの数さ
え増せば、更に大容量の負荷電流の制御が可能で、この
穐半導体固体リレーのンリーズ化が簡単に達成できる。
! In addition, since the same gate firing signal is used, as long as the characteristics of the triacs match, the load current will not be concentrated on some triacs. If the number of try books is increased, it is possible to control a larger capacity load current, and it is easy to make this solid-state semiconductor relay into a single product.

トライアック19,20は、サイリスタを逆並列接続し
たものでもよい。また、ホトサイリスタ2の点弧信号は
ホトカプラーを用いない電気信号であってもよい。
The triacs 19 and 20 may be thyristors connected in antiparallel. Furthermore, the ignition signal for the photothyristor 2 may be an electrical signal that does not use a photocoupler.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す半導体固体リレーの回
路接続図、第2図は第1図に示す半導体固体リレーの要
部における電流、電圧波形を示す図である。
FIG. 1 is a circuit connection diagram of a semiconductor solid state relay showing an embodiment of the present invention, and FIG. 2 is a diagram showing current and voltage waveforms in the main parts of the semiconductor solid state relay shown in FIG. 1.

Claims (1)

【特許請求の範囲】[Claims] 1、全波整流回路の出力端子間に第1の半導体制御整流
装置が接続され、この半導体制御整流装置には点弧手段
と全波整流回路出力電圧がほぼ零になる時にその制御端
子と一生端子間の短絡を解く短絡手段を有し、全波整流
回路の一入力端子は交流電源の一端に接続され、他の入
力端子は交流電源に接続された複数個の第2の半導体制
御整流装置の各制御端子と接続されていることを特徴と
する半導体固体リレー。
1. A first semiconductor-controlled rectifier is connected between the output terminals of the full-wave rectifier circuit. a plurality of second semiconductor-controlled rectifiers, each having a short-circuiting means for breaking a short-circuit between the terminals, one input terminal of the full-wave rectifier circuit being connected to one end of the AC power supply, and the other input terminal being connected to the AC power supply; A semiconductor solid-state relay, characterized in that it is connected to each control terminal of.
JP15378181A 1981-09-30 1981-09-30 Semiconductor solid-state relay Pending JPS5856529A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15378181A JPS5856529A (en) 1981-09-30 1981-09-30 Semiconductor solid-state relay

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15378181A JPS5856529A (en) 1981-09-30 1981-09-30 Semiconductor solid-state relay

Publications (1)

Publication Number Publication Date
JPS5856529A true JPS5856529A (en) 1983-04-04

Family

ID=15569993

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15378181A Pending JPS5856529A (en) 1981-09-30 1981-09-30 Semiconductor solid-state relay

Country Status (1)

Country Link
JP (1) JPS5856529A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5195772A (en) * 1975-02-19 1976-08-21
JPS5367847A (en) * 1976-11-30 1978-06-16 Toshiba Corp Semiconductor breaker

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5195772A (en) * 1975-02-19 1976-08-21
JPS5367847A (en) * 1976-11-30 1978-06-16 Toshiba Corp Semiconductor breaker

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