JPS5856587A - Transfer system for character multiplex signal - Google Patents

Abstract

PURPOSE:To transfer signals of different program, by picking up a digital character signal multiplexed on an input TV signal, taking the period of bit and framing, writing it in a memory and transferring the result to an output TV signal. CONSTITUTION:An input TV signal VS1 is picked up as a digital character signal at a character signal separation and pickup circuit 1 to output a timing signal TS1 phase-locked to a clock run-in. A byte synchronism detection and 1-bit error correction circuit 2 detects a framing code from the circuit 1 and a timing signal TS2 in byte synchronism. A synchronizing signal TS3 is separated at an input side synchronizing separation circuit 3. The signals TS2, TS3 are given to an input timing generation section 4 to store the data of the circuit 2 to a memory 6 via controlling circuit 5. An output TV signal VS2 is given to an output timing generation circuit 8 via an output synchronizing separation circuit 7. Based on the timing of the circuit 8, the circuit 5 reads out the memory 6 and multiplexes the information at a character multiplex circuit 9.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is characterized by
One TV signal (input T
The character signal multiplexed on the external TV signal (
This relates to a method for transferring output TV signals.

FIG. 1 is a block diagram of an apparatus implementing the invention.

The character signal of the input TV signal vsi is extracted as a dinotal character signal by a character signal separation/extraction circuit 1, and also generates a timing signal TSI phase-synchronized with a chronograph input for bit synchronization of the character signal. pie]·
The synchronization detection and l-bit error correction circuit 2 detects the framing code of the character signal separated by the character signal separation and extraction circuit l, detects the byte synchronization timing TS2''f:, and detects the 1-bit error correction code part. On the other hand, the input TV signal vSl is separated into a synchronization signal TS3 by an input side synchronization separation circuit 3.

Timing signal TSI phase-synchronized with the clock run-in of the character signal separation and extraction circuit obtained as described above.
, the timing signal TS2 phase-synchronized with the framing synchronization of the byte synchronization detection and 1-bit error correction circuit 2, and the synchronization signal TS3 of the input side synchronization separation circuit 3 are input to the input side timing generation section 4, 4, the timing necessary for controlling each part, for example, the timing of a code section for error correction of a character signal, etc. is generated. The digital character signal processed by the byte synchronization detection and 1-bit error correction 114 circuit 2 is stored in the frame 6 under the control of the 1liI group 1 circuit 5. At this time, there are two ways to write the fixed format Chrono Clan-in and framing code into the buffer f) and q lily 6, and another method where they are not written.

The TV signal of the other party to which the character 4m is transferred is output side T.
It is supplied to the device as a V signal VS2. In the output side synchronization separation circuit 7, the synchronization signal TS4 is output from the output TV signal VS2.
At separation 1~, timing is generated in the output side timing generation circuit 8 using the synchronization signal TS4, and based on this timing, the character signal is read out from the buffer anomaly 6 by the sub-leg circuit 5. That is, in the section of the line number of the output TV signal VS2 of the other party to which the character signal is to be transferred and multiplexed, the character signal stored in the computer memory 6 is read out and multiplexed by the character multiplexing circuit 9. In this case, the method of writing the chronograph-in and framing code into the buffer memory 6 is to write the chronograph-in and framing code to the buffer memory 6 at a predetermined position of the character signal, and write the chronograph-in and framing code into the buffer memory 6. In a method that does not write data into the memory 6, a preset clock run-in and framing code are read out from a storage circuit (not shown) at a predetermined position of the character signal.

Since the capacity of the buffer memory 6 differs depending on the number of character signal packets to be handled, the case of 1·g care) will be described for simplicity. All you have to do is multiply the total number of 8 pieces in the case of handling, ξ, and g.

The capacity of the buffer memo solo varies greatly depending on which of the following two conditions is selected. The first condition is
This is a case in which automatic overflow or underflow of the backup memory is allowed due to a shift in the frequency of the input/output synchronization signal, and the second condition is a case in which the above-mentioned overflow and underflow are not allowed.

As a first embodiment of the present invention, FIGS. 2 and 3 are explanatory diagrams of the over-flow and after-flow of the buffer memory when the capacity of the buffer memory is l Je kets. . FIG. 2 shows the case where the input frequency is higher than the output frequency, and the case where the 6th .9 digit is omitted is shown. In FIG. 3, the input frequency is lower than the output frequency, and the 10th packet is repeated.

Next, the buffer-f memory 8 will be described when operating under the second condition of not allowing overflow or underflow of the buffer anomaly.

In order to operate under the second condition, repeated pulling out of the device occurs and does not occur frequently.

Under the second condition, the panonoa memory capacity can be determined by the following two methods. The first method is to allocate a memory equivalent to the expected frequency shift in advance, and start reading with a delay of an amount equivalent to the expected undercut "1 -" from the input signal. This method satisfies the conditions.The explanatory diagram is the fourth embodiment as the second embodiment of the present invention.
FIG. 5 is an explanatory diagram in which, as an example, the memory capacity is 5.9 times for overflow and 5.DELTA. times for underflow. Figure 4 shows the case where the input frequency is higher than the output frequency, and Figure 4 shows the case where the input frequency is lower than the output frequency. Usually, the synchronization frequency stability of TV signals is very good. For example, if the synchronization accuracy is io"-6,
The time required to generate a phase shift is about 2 hours, so even when operating continuously for 12 hours a day, the buffer memory capacity is equivalent to ±12 packets (equivalent to 24 Akerato). It is enough.

The second method for determining the buffer memory capacity that satisfies the second condition, that is, the third embodiment of the present invention, uses meaningless information such as This method satisfies the second condition by inserting dummy signals into the input signal or output signal at appropriate intervals. According to this method, the buffer memory capacity can be reduced compared to the ml method. Diagrams explaining this operation are shown in FIGS. 6 and 7.

FIG. 6 is an explanatory diagram of the operation when the input frequency is higher than the output frequency and the buffer capacity is 2·P. Initially, the 1st and 2nd input ・ekeno]・ are read out with a delay of 2.9 notes, and the dummy ?
Control is performed so that the phase difference due to the frequency difference does not accumulate by reading out the signal after a delay of 1.e from the next one.

Next, FIG. 7 is an explanatory diagram of the operation when the input frequency is lower than the output frequency and the buffer memory capacity is 2.times. Since the reading speed of the buffer 7 memory is faster than the writing speed, even if there is a phase difference at the beginning as shown in FIG.
After extracting the character signal of ξ, at the next read timing, knowing that the write timing of the input side VSI comes after the output side timing, the second character signal of ξ is read. Insert a dummy ξ note at the next reading timing, so that the 24th character signal of the same shield message is not read out repeatedly, and an underflow of the memory is not caused. There is.

In the time charts 1. described above with reference to FIGS. 2 to 7, the frequency difference between input and output is emphasized more than it actually is. Also, cases in which the input frequency is higher than the output frequency and cases in which it is lower are written separately, but this is a meaningless explanation; the magnitude relationship between the input and output frequencies is not constant and changes over time, so The relationship can be interchanged, and the buffer memory is controlled by continuously detecting the magnitude relationship (the same applies to the phase relationship) between these frequencies.

The buffer memory phase shift 11N as explained above is carried out to transfer the character No. 15, but during this transfer, the input TV signal VSI and the output TV
The case where the field correspondence of signal VS2 corresponds to the same type of field (the relationship between Figure 8 (A) and (...)) and the case where it corresponds to different types of fields (the relationship between Figure 8 (A) and (·→)) are as follows. In the former case, the character signal is multiplexed on line number 12 of the output TV signal VS2, and in the latter case, the character signal is multiplexed on line number 275.

FIG. 9 shows a first application example using the present invention, in which characters 1.
i No. 1iXB' Self-recorded video recorder VTRI
The character signal is multiplexed to the output VS2 of the video recorder VTR2 which does not have a character signal from the TV signal output v81' of VS.
3, and by recording it on the video recorder VTR3, the character signal can be recorded and played back together with the Ike's TV 11''.In this way, when used in combination with the video recorder VTR, it is possible to edit the character signal. Money can be.

FIG. 1O shows a second application example using the present invention, and is an example of a TV signal port log sim switching device. TV signal VS4~
Switches SW4 to Sw to select any one signal of VSN
In the case of selecting N, for example, assuming that a character signal is multiplexed only on the TV signal VS4 and there are no character signals on the input signals VS5 to VSN of the other switching devices, no matter which input signal VS4 to VSN is selected, If the character signal of VS4 must always be transmitted, connect VS4 to the input VSIK in Figure 1 as shown, and connect the output selected by switch SW4 to SWN to VS2 in Figure 1. Therefore, character signals can be transmitted to the output regardless of the switching selection output.TV
Even if the signal is switched, it is possible to transmit the 11,000-character character, so if this switching device is used to switch the relay program of a relay line, and the transmission route switching logic for TV signals and character signals is different, this is also true. By using combinations of applications, different switching logics can be used.

Next, FIG. 11 is a third application example using the present invention, and is a connection diagram in which a device according to the present invention is inserted in the middle of a transmission line to shape the waveform of a character signal part, and is a connection diagram for input TV signals. is V
Supplied to SI and VS2, same TV signal as input,
The character signal extracted from the input signal is corrected for l-bit errors by the byte synchronization detection and 1-pin l-error correction circuit 2 shown in FIG.
If the signal transmission path is long distance, by inserting this device in an appropriate section, it is possible to transmit the character signal portion without degrading the S/N or increasing the transmission error rate. be.

According to the present invention, a character (ij number) can be inserted into any line number -H4 during the vertical retrace period of the TV signal, so that it is possible to insert a character (ij number) into any line number -H4 during the vertical retrace period of the TV signal. Even for signals, if there is an empty line number, change the empty line number to 1 so that a character signal can be added there.
It can also be used to easily integrate teletext zolograms produced in different zoroses.

[Brief explanation of drawings]

FIG. 1 is a detailed block diagram of the present invention, and FIGS. 2, 3, 4, 5, 6, and 7 are explanations of memory operations of embodiments of the present invention. Figure 8 is a waveform diagram for explaining the operation of the embodiment of the present invention, Figures 9, 10, and 11 are waveform diagrams for explaining the detailed explanation of the present invention. error correction circuit, 3... input side synchronization separation circuit, 4... input side timing generation circuit, 5... control circuit, 6... buffer memory, 7...
Output side synchronous separation circuit, 8...Output 111j timing generation circuit, 9...Character 1, 1 matron heavy circuit. Patent Applicant Oki Electric Industry Co., Ltd. Figure 1 57.48 11 (3W <January 1-l Patent g' to the Director General) 1981 Patent Application No. 153731 No. 7, Contents of Amendment (1) In the detailed description, page 5, lines 9 to 10, it says, ``You just have to do it...'' [If you are handling multiple... (2) In the 2nd line of page 10 of the same book, the text ``from VSI'' is corrected to ``From rvsx.'' (3) In the 3rd line of page 10 of the same book, ``output VS2'' is corrected. Supplement that to "output VS2 of VSI".

Claims (2)

[Claims] (1) In the method of transferring the character signal multiplexed on the input side TV signal to the output side TV signal, the Dinotal character signal consisting of a header part and information data part multiplexed on the input TV signal is extracted, and the corresponding character Synchronize the bits and framing of the character signal using the chronoclone and rooming codes inserted in a part of the header of the signal.
After performing error correction on the error correction code of the character signal, and writing the data other than the error correction code in the character signal into the memory together with the fixed data chronocrane-in and framing code without error correction, A character multiplex signal transfer method characterized in that the memory is read out using a clock signal phase-synchronized with the output TV signal IKI and transferred to a specified line number of the output TV signal. (2) In a method in which the character signal multiplexed on the input side TV signal is transferred to the output side TV by 4%
Extract all of Dinotal's garbled characters, which consist of the header part and information data part multiplexed with the signal, and add the following part of the character signal (・'C) by inserting the Chrono Clan-in and the framing code 1・゛. The bits and framing of the character signal are synchronized, error correction is performed on the error correction code of the previous character signal, data other than the error correction code is written to memory without error correction, and the data is written to the memory without error correction. The fixed date of the CL/IN and framing code can be read out from another self-memory circuit set in advance using a phase synchronized signal on the output TV signal side, thereby specifying the output TV signal. A character multiplex signal transfer method characterized by transfer to line numbers.