JPS586190B2 - Vending machine coin acceptor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a coin accepting device for a vending machine, and particularly to control when coins are continuously inserted.

2. There are various coin acceptance devices for vending machines equipped with a coin detection device that determines the authenticity of inserted coins by disposing a plurality of coin detectors that individually detect the properties of various coins along a coin inspection path. Although it has been proposed, in such a coin receiving device for a vending machine, the genuineness of a coin is determined for the first time by the output of the single coin detector at the final stage, and the acceptance of the inserted coin is controlled.

In other words, the inspection results of the detectors in the previous stage than the final stage coin detector are stored in an appropriate storage circuit such as a flip-flop, and when the test results of the final stage detector are obtained, the results of the previous tests including that one are stored. It is configured to accept the input coins as genuine coins only when all the results are genuine coins.

By the way, in such a coin accepting device of a vending machine, while the previously inserted coin is still passing through the coin inspection passage and being inspected by one of the detectors, another coin inserted next may If a coin enters the inspection passage and is inspected by any detector, it will not be possible to accurately determine authenticity.

The present invention was made in order to cope with the above-mentioned situation, and is designed so that the subsequently inserted coin passes through the first stage coin detector before the first inserted coin passes through the last stage coin detector. To provide a coin receiving device for a vending machine which detects continuous insertion of coins and refuses to accept subsequent coins inserted.

Therefore, in the present invention, when coins are continuously inserted as described above, the device is reset and the continuously inserted coins are returned. The present invention is characterized in that a timer having an operation time corresponding to the time required to pass through the detectors (from the last detector to the last detector) is provided, and the reset is canceled by the output of this timer.

The operation time of the timer starts when the input coin enters the first stage detector, and the next coin (due to continuous input) starts when the input coin enters the first stage detector during the operation time regarding the previous coin. When the switch is entered, the previous operating time is canceled and a new operating time is started again.

Therefore, in the case of continuous coin insertion, the reset is canceled only when the timer time has elapsed since the last coin insertion.

This means that the reset is performed until the last coin of the continuously inserted coins has definitely passed through the coin inspection passage (equivalent to the timer time) and is guided to the return passage, ensuring that continuously inputted coins are definitely removed. This has the effect of making it possible.

Of course, if coins are inserted at intervals longer than the timer operation time, the device of the present invention operates normally.

Although the characteristic outline of the present invention has been described above, one embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

In FIG. 1, a coin inserted through a coin input port 1 passes through a thickness check screw 2 and enters a coin inspection passage 3.

By adjusting the amount of protrusion of the tip of the screw 2 into the coin passage, the thickness of the coin entering the coin inspection passage 3 is regulated, and counterfeit coins that are thicker than genuine coins are stopped by the screw 2. It will be done.

A thread cutting protrusion 4 with a sharp tip protruding into the coin passage in front of the coin inspection passage 3 is used to prevent selling goods from being fraudulently stolen by inserting coins suspended by a thread from the input slot 1.

Three coin detectors 5, 6, and 7 are arranged in order in the coin inspection passage 3.

The first stage coin detector 5 is for detecting the coin diameter, and has a primary coil 5a and a secondary coil 5b (see Figs. 2 and 4).
(see figure), and as shown in Fig. 2, the magnetic flux Δ is almost perpendicular to the radial direction of the coin to be inspected 8 falling in the coin inspection passage 3 (almost perpendicular to the radial surface). Coils 5a and 5b are arranged in relation to each other.

Therefore, the larger the coin diameter is, the more the magnetic flux is cut off, and a detected waveform having a peak value (in this case, a negative peak) corresponding to the coin diameter is obtained from the secondary coil 5b.

For example, the postal cargo detectors 6 and 7 in the latter stage are disclosed in Japanese Patent Application No. 47-6811.
A differential transformer type coin detector as described in the specification of No. 1 is used to test different coin properties.

For example, one coin detector 6 inspects the material of the coin, and the other detector 7 inspects the surface pattern shape of the coin.

For this reason, the excitation frequency f2 of the primary coil 6a (see FIG. 4) of one coin detector 6 is set to a frequency that makes it easy to detect the coin material, and the primary coil 7a of the other detector 7 (see FIG. 4) is set to a frequency that makes it easy to detect the coin material. ) is set as a frequency at which the coin surface pattern shape can be easily detected.

When the coin passes through the coin detector 7 at the final stage, the authenticity check is completed, and if the coin is genuine, the acceptance solenoid 9 (see FIG. 3) is energized and the acceptance protrusion 10 is sucked in the direction of arrow A.

An opening 11 located below the end portion of the coin inspection passage 3 is normally open toward the return passage 12, and only when the nolenoid 9 is energized by detection of a genuine coin, the protrusion 10 enters the opening 11 to return the coin. Block the entrance to passage 12.

Therefore, only when the solenoid 9 is energized, the coin coming out of the coin inspection passage 3 is guided to the genuine coin passage 13 and accepted, and at other times, the coin passes through the opening 11 to the return passage 12 located below the passage 13. The coin is guided and returned to a return slot (not shown).

The circuit shown in FIG. 4 controls the coin-accepting operation in the mechanism of FIG. 1, and provides a counting pulse to the input amount counter when a coin is accepted.

The oscillator 14 is the primary coil 5a-7 of each coin detector 5-7.
The frequency f1 is always supplied to the coin diameter detector 5, but power is supplied to the coin detectors 6 and 7 via gates 15 and 16. Can be switched.

Two differential transformer type detectors 6 and 7 connected in series with opposite phases
The detection signals outputted from the two secondary coils 5b, 5c and 7b, 7c are applied to detection amplifiers 17, 18, and the alternating current components are removed and input to an OR circuit 19.

The detection output from the secondary coil 5b of the coin diameter detector 5 is applied to the detection amplification and phase inversion amplifier 20, where the alternating current component is removed and the negative peak waveform is inverted to the positive peak waveform.

In this embodiment, since the coin detection waveform of the detector 5 is obtained as a valley-shaped attenuated waveform, this is inverted to a mountain-shaped waveform.

The detection signal from the coin diameter detector 5 is applied to a comparator 22.23 via a line 21 and appears on a line 240 via an OR circuit 19.

Therefore, in response to a single coin passing through the coin inspection path 3, the secondary coils 5b, 6b, 6 of each coin detector 5, 6.7
Since the detection waveforms occur in order in c, 7b, and 7c, only the coin diameter detection waveform 5b' of the detector 5 appears on line 21, as shown in FIG.
As shown in FIG. 7e' appears in order.

The detected waveforms 5b' to 7c/ of the line 240 are the comparators 24 to
29, and are compared with reference levels set in each of the comparators 24-29.

The comparators 22 and 23 detect that a coin has entered the coin diameter detector 5, and the lower level (near the bottom) of the coin diameter detection waveform 5b/ is the set reference level.

The reference level e1 of the comparator 22 is somewhat higher than the reference level e2 of the comparator 23 (see FIG. 5a).

It is assumed that the comparators 22 to 29 output a signal 1J1 when the level of the input coin detection waveform becomes higher than the set reference level.

Therefore, the level of the coin diameter detection waveform 5b' is the reference level e.
When it becomes higher than 1, the comparator 22 outputs the signal 111,
Set the Flimp Flossop 30.

Further, when the level of the detected waveform 5b' becomes lower than the reference level e2, the output of the comparator 23 changes to "0".

Therefore, the flip-flop 30 is reset via the inverter 31, and the output of the flip-flop 30 is as shown in FIG.
As shown in FIG. 3, the waveform approximately corresponds to the time width of the coin diameter detection waveform 5b/.

Comparator 24 has the same function as comparators 22 and 23.
．． 25, and the respective reference levels e3 and e4 are levels near the bottoms of the mountain-shaped detection waveforms 5b' to 70', and the levels are somewhat different.

As will be described later, when the coin diameter detection waveform 5b/ is generated, the reference level e3+64 is not applied and the comparators 24 and 25 do not operate.When the upper reference level e3 is exceeded, the flip-flop 32 is activated. If the lower reference level e4 is exceeded, it will be reset.
As shown in , the output of the flip-flop 32 approximately corresponds to the time width of the coin detection waveforms 6b', 6c', 7b', and 7c'. Level e1+63 to set flip-flop 30.32 and level e2, e to reset
4 are different, a hysteresis characteristic is provided between the setting and reset of the flip-flops 30 and 32.

Therefore, even if the coin detection waveforms obtained from the coin detectors 5, 6, and 17 are distorted, a pulse can be accurately obtained from the flip-flops 30 and 32 for each detected waveform.

Set flip-flop 30.32 at one level,
If the coin detection waveform is reset, the coin detection waveform will be disturbed, and when the set/reset level is raised and lowered in small steps, the setting and reset will be repeated frequently, resulting in a large number of pulses per detection waveform.

To prevent this, it is extremely effective to use two reference levels e1, e2 or e3te4 as in this embodiment.

The comparators 26, 27 and 28, 29 are each paired as a window circuit 33 for determining the peak level of the coin detection waveform.
．． 34 upper and lower threshold levels are set.

For example, if the window circuit 33 is for detecting the peak level of the 10 yen coin detection waveform, the upper limit reference level H1 set in the comparator 26 sets the upper limit value of the peak level of the 10 yen coin detection waveform. The lower limit reference level L1 set in the comparator 27 is used to set the lower limit value of the peak level of the 10 yen coin detection waveform.

Further, assuming that the window circuit 34 detects the peak level of the 50 yen coin detection waveform, the reference level H2 of the comparator 28 is the upper limit value of the peak level of the 50 yen coin detection waveform, and the lower limit Comparator 2 is the one with the value set.
This is the reference level L2 of 9.

Each of the reference levels H1, L1, H2, L2 is sequentially switched to a value corresponding to the coin properties to be inspected by the coin detectors 5, 6.7 as the coin passes through the coin detectors 5, 6.7.

Taking the 10 yen coin window circuit 33 as an example, as shown in FIG. 5C, the upper limit reference level H1 and the lower limit reference level L1 are sequentially switched as shown in the table below in response to the detected waveforms of various properties. .

Similarly, the upper limit reference level H2 of the window circuit 34 of the 50 yen coin
and the lower limit level L2 is also 3 corresponding to the detected waveform of each coin property.
The values are sequentially switched to the correct values (e111el2...e16).

Reference levels e1 to e4, H1 to L of each comparator 22 to 29
2 (e5 to e16) are supplied from the reference voltage generation circuit 35.

Since the values of the reference levels H1, L1 or H2, L2 are switched in order, only one window circuit 33 or 34 is enough.0 Now, the output 11'' of the flip-flop 30 (FIG. 5b) generated when a coin enters the first coin detector 5 satisfies the condition of the AND circuit 36 and sets the flip-flop 37.

The other inputs of the AND circuit 36 are the reset side output of the flip-flop 37 and the receiving solenoid disconnection detection signal 100, which are normally "1", so that the conditions of the AND circuit 36 are satisfied.

When the coin acceptance solenoid 9 is disconnected, the signal 100 is 1.
01, the AND circuit 36 is rendered inoperative, and the operation of the circuit shown in FIG. 4 is prohibited, so that no counting pulses are generated.

The set output of flip-flop 37 is applied to line 38 and sets flip-flop 39.

When the set output 11'' of the flip-flop 39 rises, the timer 40 is set and the timer operation starts.

During the operation time T1 of the timer 40, the inserted coin is in the coin inspection passage 3.
That is, the time to complete passing through all the coin detectors 5, 6.7, that is, the time approximately equivalent to the coin inspection completion time (see FIG. 5).

When the timer 40 operating time T1 ends, the timer 40 generates an output 11, which resets the flip-flop 37 via the OR circuit 41.

Therefore, the time when line 38 becomes signal 11'' is determined by timer 40.
This is equivalent to the operating time T1.

In addition, the timer 4 is connected via an AND circuit 42 and an OR circuit 43
The flip-flop 39 is reset by the output ゜1'' of 0.

On the other hand, when the output of flip-flop 30 becomes 11,
The condition of the AND circuit 49 is satisfied by the set output 11'' of the flip-flop 37 and the reset output ``1'' of the flip-flop 48.

The output 1l'' of the AND circuit 49 causes the line 50 to become a signal ``1'', which is then passed through the OR circuit 51 to the shift register 5.
The signal 11" is read into the first stage R1 of the second stage R1.

Then, when the coin finishes passing through the first coin detector 5, the output of the flip-flop 30 falls to 10" (Fig. 5b).
), one pulse is generated from the falling pulse generation circuit 44 at the time of falling.

The falling pulse generating circuits 44, 45, 46, and 47 are circuits that generate one short pulse when the input signal power falls from 1'' to ``O''.

The output pulse of the falling pulse generating circuit 44 sets the flip-flop 48 and also resets the flip-flop 54 via an AND circuit 520 and an OR circuit 53.

Further, the output 10'' of the AND circuit 49 becomes the signal power Q// of the line 50.

The signal on line 50 therefore corresponds to the output of flip-flop 30 (FIG. 5b).

The signal on line 50 is applied to an AND circuit 55.56;
It is possible to memorize the coin diameter inspection results.

Therefore, the signal 111 on line 50 is the coin diameter inspection period TE.
Corresponds to 1.

The operation will be explained with reference to the window circuit 33. The output of the upper threshold comparator 26 is applied to the NOR circuit 57, and the output of the lower threshold comparator 27 is applied to the set input of the flip-flop 58.

The level of the coin diameter detection waveform 5b/ is at the lower limit reference level Ll (
eQ), the flip-flop 58 is set,
The reset output page becomes '0''.

The peak level of the detected waveform 5b' is the upper limit reference Hl (e5)
If the value is not exceeded, the output of the comparator 26 will be 10'', and the output of the NOR circuit 57 will be 11''.

When the detection waveform 5b/ is almost completed, the flip-flop 30 is reset, so its reset output 11'' resets the flip-flop 58 via the AND circuit 59.
The output of the NOR circuit 57 is set to 10".

Therefore, one pulse is generated from the falling pulse generation circuit 46 and input to the AND circuits 55 and 60.6l.

Now is the coin diameter inspection period TE1 (or just before it ends)
Therefore, the signal on line 50 is 11", and the signal on line 3 is
Since the signal of 8 is also 11", the falling pulse generation circuit 4
The output pulse No. 6 sets a 10 yen coin diameter storage flip-flop 63 via an AND circuit 55 and an AND circuit 62.

Therefore, when the diameter of the coin is verified to be a genuine coin, 11'' is stored in the flip-flop 63.

By the way, if the peak level of the detected waveform 5b/ does not fall between the upper and lower thresholds H1, L1 (e5, e6), especially if the peak level exceeds the upper reference level H1 (e5), the comparator 26 The output voltage becomes 111, and the output of the NOR circuit 57 falls to 10''.

When the peak of the detected waveform 5b' falls, the output of the comparator 26 becomes 10'', the output of the NOR circuit 57 rises to 1 again, and the reset output 2 of the flip-flop 58
1'' causes the output of the NOR circuit 57 to fall to '0'' again.

Therefore, when the peak of the detection waveform 5b/ is higher than the upper reference value H1 of the window circuit 33 (or 34), two or more pulses are generated from the falling pulse generation circuit 46 during the coin inspection period TE1.

In this case, the first pulse causes flip-flop 63
is set, but the AND circuit 64 is set by the next pulse.
The flip-flop 63 is reset via the .

All the flip-flops used in this embodiment, including the flip-flop 63, are "reset priority flip-flops."

Therefore, the flip-flop 63 is preferentially reset by two pulses (even if the set input is applied at the same time). Even if two or more pulses occur during period TE1, the second pulse resets the AND circuit. Since the flip-flop 54 is set via the flip-flop 64 and its reset output becomes "0", the third and subsequent pulses are blocked when the condition of the AND circuit 62 is not met.

Therefore, if the peak level of the coin detection waveform does not fall within the upper or lower threshold of the window circuit, the test result storage flip-flop 63 (or 64, 65, 66, 67, 68
．． The memory of 69) is '0〃.

Therefore, the flip-flop 54 functions substantially in conjunction with the determining operation of the window circuits 33, 34.

The signal "1" of the first stage R1 of the shift register 52 is applied to the gate 15 and the reference voltage generation circuit 35 via the OR circuit 70, and supplies the excitation frequency f2 to the primary coil 6a of the coin detector 6 via the gate 15. do.

In this way, the second coin detector 6 becomes capable of detecting operation, and generates detection waveforms 5b/ and 6C/ in response to a coin falling from the coin detector 5 along its diameter.

At this time, the reference voltage generation circuit 35 receives the AC signal f2 supplied to the coil 6a through the gate 15, and based on this signal f2, the reference voltage generation circuit 35 receives the DC reference voltage e71e81el31.
el4 and outputs H in response to the signal from the OR circuit 70.
1, L1, H2, L2 values as these voltages e71egl
Switch to e131el4.

Further, when AC signal f2A or f3 is applied, reference voltages e3 and e4 are supplied to comparators 24 and 25.

As shown in FIG. 5d, pulses approximately corresponding to the time width of the coin detection waveform 6b'A60' are output from the flip-flop 32, and the falling pulse generation circuit 45 generates one short pulse in response to the falling edges of these pulses. Output.

At this time, since the signal on line 50 is already 10, the AND circuit 7 has an inhibit gate for the signal on line 50.
1, a pulse is output in response to a falling pulse, and the signal 11'' of the first stage R1 of the shift register 52 is shifted to the next stage via the OR circuit 51.

The shift register 52 receives the first read single signal ``1''.
The configuration is such that " is sequentially shifted by a pulse from an OR circuit 51."

Therefore, when the detected waveform 5b/ almost ends, the signal "1" becomes 2.
It is shifted to the second stage R2.

The output 11'' of the stage horse 2 continues the f2 excitation of the primary coil 6a via the OR circuit 70 and provides a signal 11'' on the line 72.

The window circuit 33 or 34 operates in the same manner as described above to inspect the peak level regarding the material, and outputs one pulse per detected waveform in the case of genuine coins.

When the peak level of specie is detected with respect to the detection waveform 60', the line 72 is the signal 11'', so the AND circuit 60
(or 73 in the case of 50 yen), and the signal ``1'' is sent to the flip-flop 65 (or 68 in the case of 50 yen) for storing the inspection result of the 10 yen coin material via the AND circuit 78 (or 79).
to remember.

When the coin detection waveform 60' almost ends, the signal "1" of the shift register 52 is shifted to the third stage R3 by the output pulse of the falling pulse generating circuit 45.

Therefore, gate 15 becomes inoperative. Further, the flipflop 54 is reset via an AND circuit 74 having an inhibit gate for the signal on line 50 almost every time the detected waveform is completed.

The signal 1l'' of the stage R3 is passed through the OR circuit 75 to the gate 16.
and the reference voltage generating circuit 35, and supplies an excitation frequency f3 to the primary coil 7a of the coin detector 7 via the gate 16.

In this way, the last detector 7 becomes capable of detecting operation, and the detection waveform 7 is generated in response to the falling coin with the diameter of the coin detector 6.
Generate b' r 7 c'.

At this time, the reference voltage generation circuit 35 receives the AC signal f3 supplied to the coil 7a via the gate 16, and generates the DC reference voltage e9 t e10 1 based on this signal f3.
el5 1 eta, and the values of the outputs H1, L1, H2, L2 are changed to these voltages e9, el. o, el5, el6.

Therefore, a pulse is generated from the flip-flop 32 in response to the coin detection waveform 7b'l7C' (FIG. 5d), and the window circuit 33
．． In step 34, a peak level inspection regarding the shape of the coin surface pattern is performed.

One pulse outputted from the falling pulse generation circuit 45 corresponding to almost the end of the detected waveform 7b/ is sent to the shift register 5.
2's signal 11" to stage R4, and the signal 1" to line 76.
Give 1〃.

Therefore, when the peak level of specie is detected with respect to the detection waveform 70', the condition of the AND circuit 61 (or 77 in the case of 50 yen) is satisfied, and the condition of the AND circuit 80 (or 81
) to the coin surface pattern shape inspection result storage flip-flop 66 (or 69 in the case of 50 yen) is sent a signal "I"1".
remember.

When the last detected waveform 70' is almost finished, the output of the falling pulse generation circuit 45 causes the signal ``1'' of the shift register 52 to change.
" is shifted to the final stage R5.

Therefore, the gate 16 becomes inactive, and only the excitation frequency f1 is applied to the primary coil 5a of the coin detector 5, waiting for the next coin to arrive.

Also, is the reference voltage generated? Path 35 is the first stage coin detector 5
When only the AC signal f1 applied to the primary coil 5a is input, that is, the signals from the OR circuits 70 and 75 are both '
0'', the reference voltage e is set based on the AC signal f1.
1, e2, e5, e6, e1, e1 and comparators 22, 23 . 26-29.

Now, when the operating time T1 of the timer 40 ends, the signal on the line 38 becomes '0' as described above, but at this time the coin inspection has already been completed and the flip-flop 63.6
The test results are stored in 5.66 or 67.68, 69.

If the three coin properties tested are all genuine coins, and if they are 10 yen coins, use Fritz Frilop 6.
3, 65, and 66 are all 11", and the output of the AND circuit 82 is 91".

Also, if it is a 50 yen specie, flip-flop 67
The outputs of ~169 are all 11", and the AND circuit 83
The output of is 11''.

The output of the AND circuit 82 is applied to the inhibit gates of the AND circuits 84 and 85, and the output of the AND circuit 83 is applied to the inhibit gates of the AND circuits 85 and 84, respectively, so that genuine coin signals of different coins are output simultaneously. There is no such thing.

The other inputs of the AND circuits 84 and 85 are shift registers 5
The AND circuits 84 and 85 become operational when all the coin inspections are reliably completed.

AND circuit 84. The output "1" of 85 is a genuine coin detection signal, indicating that the inserted coin should be accepted.

These outputs are outputted through AND circuits 86 and 87, respectively.
The input data is input to the inserted yen coin counter 88 and the inserted 50 yen coin counter 89, and the number of inserted coins is calculated.

The counts of the counters 88 and 89 are used in a vending control circuit (not shown) of the vending machine for vending operations, change dispensing operations, and the like.

In addition, the outputs of the AND circuits 84 and 85 are output from the input sheet number control section 9.
When the maximum number of coins in one coin insertion operation is exceeded, the output of the control unit 90 becomes 10'', and subsequent coins are prohibited from being accepted even if they are genuine coins.

The control section 90 outputs 1'' only when genuine coins are accepted, and outputs 10'/ when coins are not accepted due to counterfeit coins or an excess number of coins.

Further, the specie acceptance signal from the AND circuits 84 and 85 is passed through the OR circuit 91 and the AND circuit 92 to the flip-flop 9.
Set 3.

The set output of flip-flop 93 is applied to AND circuit 94, sets flip-flop 95, and starts operation of timer 96.

The output of the timer 96 is normally ``XO'' and becomes 11'' when the timer operation time ends.

Therefore, the AND circuit 94, in which the output of the timer 96 is added to the inhibit gate, becomes the output 11 at the same time as the flip-flop 93 is set, and the receiving solenoid 9 (
(see Figure 3).

This energization of the solenoid 9 continues until the operating time of the timer 96 expires, so that as soon as the coin passes the last detector 7, if it is a genuine coin, the receiving protrusion 10 attracted by the solenoid 9 Blocking the opening 11 of the coin passage,
Coins are accepted in the specie passage 13.

(See Figure 1).

The operating time T2 of the timer 96 corresponds to the time interval between coins when genuine coins are continuously inserted without double insertion.

When the next coin comes to the position of the coin detector 7 during the operation time of the timer 96 and the stage R4 of the shift register 52 becomes the signal 11", the signal 9l" is applied to the reset input of the flip-flop 95, indicating that reset is given priority. Force a reset.

If the coin is a genuine coin, the input signal 11'' of the flip-flop 95 is applied, so as soon as the reset input falls to 10'', the flip-flop 95 is set, and the input of the timer 96 rises, so the operation time of the timer is restarted. It starts from the beginning.

Therefore, when coins (genuine coins) are continuously inserted, the output of the timer 96 is 10'' without interruption, and the solenoid 9 continues to be energized. In the case of a coin, the output of the AND circuit 106 (inhibited by the output 10" of the control section 90) becomes 11" due to the output of the stage R5 of the shift register, the flip-flop 93 is reset, and the flip-flop 95 is not set.

When the operating time of timer 96 ends, the condition of AND circuit 97 is satisfied and flip-flop 93 is reset via OR circuit 98.

If the receiving solenoid 9 does not operate due to a failure, a signal 11'' is applied to the line 99, a flip-flop 101 is set via an AND circuit 100, and a failure signal ST is output.

Note that the output of the final stage R of the shift register 52 is applied to a reset signal register (not shown) via a delay circuit 102 to generate a reset signal.

This reset signal is used to reset the memory of each flip-flop of the coin receiving device shown in FIG. 4, and the reset signal is output every time one coin is inspected.

Next, prevention of double input will be explained.

If the previously inserted coin is still in the coin inspection path 3, there is a signal 11'' in any of stages R1 to R4 of the shift register 52, and stage R is "0".

Therefore, the inhibit gate of the AND circuit 103 includes stage R,
The signal applied from is 10".

Further, when the coin diameter inspection period TE1 of the previously inserted coin has ended, the output of the AND circuit 49 is 10'', which is added to the other inhibit gate of the fund circuit 103.

When the next coin enters the coin inspection passage 3 in this state, the output of the flip-flop 30 becomes 1,
The output of the AND circuit 103 becomes 11.

In this way, when double input is detected, the AND circuit 103
sets the flip flip flop 104, and this set output is applied to the reset signal register (not shown) to generate a reset signal (not shown).

This reset signal causes each flip-flop (
In particular, the flip-flops 63 to 69) are reset and no coin inspection/discrimination operation is performed.

Therefore, the receiving solenoid 9 is not energized and all double-inserted coins are returned to the return path 12.

When the last coin of the double input coins passes through the first detector 5, the output '1'' of the AND circuit 105 is output to the OR circuit 43.
However, when the output of the OR circuit 43 returns to 10'', the flip-flop 37
Since the output is 1", the flip-flop 39 is set immediately.

Therefore, the timer 40 returns the timer operation to the beginning upon the rise of the output of the flip-flop 39, and restarts the operating time T1.

As a result, the operation of the timer 40 continues during the double insertion of coins, and the original operation time T1 of the timer 40 starts from the time when the last double-inserted coin enters the coin inspection passage 3.
The timer operation ends when the timer elapses and an output '1'' is produced.

This output '1' is applied to the reset input of the flip flip flop 104 and releases the generation of the reset signal.

Therefore, the flip-flops 63, 65 to 69, etc. of the circuit for inspecting and determining coins are released from reset and can operate normally.

In this way, since the operation of the timer 40 is extended, the normal operation of each circuit in FIG. 4 is started after the last double-inserted coin has definitely entered the return passage 12 .

In addition, in the above example, the coins to be inspected are 10 yen and 50 yen.
Although the example is made of yen, it can be applied to any type of coins.

In the above embodiment, a transformer type detector is used as the coin diameter detector 5, but a differential transformer type detector having two secondary coils connected in series and in reverse phase may also be used.

Further, instead of the shift register 52, a counter and a decoder or a counting circuit formed by combining a plurality of flip-flops and logic gates can be used.
In short, any sequential control circuit is sufficient.

[Brief explanation of drawings]

Fig. 1 is a schematic structural explanatory diagram showing an embodiment of the device of the present invention in terms of mechanical parts, Fig. 2 is a diagram illustrating an example of the configuration of a coin diameter detector, and Fig. 3 is a diagram showing the line 1-■ in Fig. 1. Schematic sectional view, 4th
The figure is a block diagram showing an embodiment of the device of the present invention in terms of circuit parts, and FIG. 5 is an output waveform timing chart of each part of FIG. 4. 1... Coin slot, 3... Coin inspection passage, 5... Coin diameter detector, 6, 7...
Coin detector, 9... Acceptance solenoid, 12...
...Return passage, 13... Specie acceptance passage, 1
4... Oscillator, 22-29... Comparator, 33.34... Window circuit, 35... Reference voltage generation circuit, 40.96... ...Timer, 52
...Shift register.

Claims (1)

[Scope of Claims] 1. A coin detection unit including a plurality of coin detectors arranged along a coin path to individually detect various coin properties, and determining the detection output of each of the coin detectors, A determination circuit that integrates the results of each determination and determines whether the coin is genuine or counterfeit; and a determination circuit that is located in the rear passage of the coin detection section and is energized only when the determination circuit sends out a genuine coin determination output to detect the counterfeit coin passage. A coin sorting electromagnetic device that closes and guides the specie coins to the specie passageway, and a coin sorting device that allows the subsequent coins to pass through the coin detector in the first stage before the previously inserted coin finishes passing through the coin detector in the final stage. In the case of continuous input coins that operate, there is a continuous input coin acceptance rejection device that prohibits the judgment operation of the judgment circuit and suppresses the operation of the electromagnetic device to refuse acceptance of the input coins, and a continuous input coin acceptance rejection device that rejects the input coins. The operation starts when the coin reaches the coin detector of the stage, has an operation time at least equivalent to the time required for the coin to pass from the first stage to the coin detector of the last stage, and after the end of the operation time, the continuous operation starts. 1. A coin accepting device for a vending machine, comprising: a timer circuit for canceling a prohibition of a determination operation of the determining circuit by an input coin acceptance rejecting device. 2. The timer circuit extends the operating time by the time required for the subsequent coin to pass through the final stage coin detector if a subsequent coin activates the first stage coin detector during the operating time. . A coin accepting device for a vending machine according to claim 1.