JPS5873263A - Bnzs decoding and error detector - Google Patents

Abstract

PURPOSE:To reduce the scale of a decoding and error detection circuit, by separating a reception signal of a BnZS signal into positive and negative pulses, and outputting each pulse train, and detecting the bipolar error where pulses having the same polarity are consecutive. CONSTITUTION:A reception input signal (c) is separatingly outputted 1 into the 1st pulse train (d) corresponding to a positive pulse and the 2nd pulse train (e) corresponding to a negative pulse. The 1st and 2nd pulse trains are coupled with an OR circuit 7 and inputted to the 1st shift register 3, and the output state of a bipolar error detection circuit 6 detecting the bipolar error is stored in the 2nd shift register 9 from the 1st and 2nd pulse trains. The state of each stage output of the 1st and 2nd shift registers is compared with a prescribed pattern to detect a zero replacing pattern and the said 1st and 2nd shift registers are cleared through the detection of the zero replacing pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to BnZS code O decoding and bivot error detector.
When a code is present, the n "0" codes are replaced with a bipolar signal having a fixed pattern and containing bipolar errors, and the code is sent out. Transmission code medium K
When n "0"' codes are not consecutive, a bivotes pulse with inverted polarity is output at every 11" in the transmission code, just like a normal bipolar signal, and
For 1, there is no output pulse. When decoding the received signal, the transmitted code can be restored by detecting the certain pattern from the received signal and decoding it by replacing it with n consecutive @O''.

With the above configuration, 10
The BnZS code solves the difficulty in extracting the timing signal on the receiving side, which occurs when " is continuous." That is, the BnZS code is used to improve the drawbacks of ordinary bipolar signals.

FIG. 1 is a block diagram showing an example of a conventional BnZS decoder and error detector. That is, the received input signal C is separated into a positive pulse and a negative pulse by the conversion circuit 1. Then, a first pulse train d is output in response to a positive pulse, and a second pulse train d is output in response to a negative pulse.

The first pulse train d t is input to the n-stage shift register RK, and the pulse train 2 of the second stage is input to the first stage shift register 8. These shift registers perform a shifting operation based on a timing signal generated from a received input signal C by a tie extraction circuit (not shown). The outputs of each stage of the shift registers 2 and 8 are input to zero substitution pattern detection circuits 4 and 5, and the zero substitution pattern detection circuits 4 and 5 detect the zero substitution pattern by comparing the input signal with a certain pattern. do. The outputs of pattern detection circuits 4 and 6 are input to OR circuit 7, and shift registers 2 and 8 are cleared by the output of OR circuit 7.

Final stage outputs d' and e' of shift registers 2 and 8
can be combined by an OR circuit 8 to restore the transmitted code to the output of the OR circuit 8. On the other hand, the final stage outputs d' and e' of the shift registers 2 and 8 are connected to a bipolar error detection circuit 6. The bipolar error detection circuit 6 inputs the above two input signals d' and e' alternately @
If it is not "1", in other words, if @1" is input continuously from either input signal, an error detection signal is output. The above configuration operations enable BnZS decoding and bipolar error detection.

However, in the conventional circuit described above, as the value of n of the BnZS code increases, the number of stages of shift registers 2 and 8 increases.
Since the number of bits of the detection pattern becomes large, there is a drawback that the circuit scale increases.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional drawbacks and provide a BnZS decoder and error detector with a small circuit scale.

The decoding error detector of the present invention separates the received signals of the BnZs signal into a positive polarity pulse and a negative polarity pulse, and
and a bipolar error detection circuit that detects a bipolar error in which consecutive pulses of the same polarity occur.
In the BnZ8 decoding and error detector, which outputs a decoded output in which the first and second pulse trains output from the conversion circuit have a fixed pattern, the output is changed to n consecutive 10'' codes, and the output of the conversion circuit is an OR circuit that inputs the first and 1sg pulse trains to be input, a first shift register of the An stage that inputs the output of the OR circuit, and an a bipolar bounce detection circuit that outputs an error detection signal when the first and second pulse trains are not input alternately; a second shift register that stores the output state of the output signal of the bipolar bounce detection circuit; Zero replacement pattern detection for inputting the output of each stage of the shift register and the output of each stage of the first shift register, and clearing the first and second shift registers when both inputs have a certain pattern. equipped with a vessel,
The final stage output of the first shift register is used as a decoded output, and the bipolar error detection signal is obtained from the final stage output of the second shift register.

Next, one aspect of the present invention will be explained in detail with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention.

That is, the conversion circuit l inputs the received signal C, separates it into positive polarity pulses and negative polarity pulses, and generates a first pulse train d corresponding to the positive polarity pulses and a second pulse train d corresponding to the negative polarity pulses. Output e. The bipolar error detection circuit 6 inputs the first pulse train d and the second pulse train . Output. On the other hand, t! The pulse train d of i1 and the second pulse train are combined by the OR circuit 7, and the OR circuit 7
The output signal f is inputted to the n-stage first shift register 8. The shift register 8 performs a shift operation in response to a timing signal bK output from a non-illustrated input tie construction extraction circuit. On the other hand, the error detection signal g output from the error detection circuit 6 is input to the shift register 9 of #I2 to store the state of the output of the error detection circuit 6. The second shift register 9 performs a shift operation every time the output signal f of the OR circuit 7 falls. Output Q of each stage of the second shift register
, . The signal then goes to the output of the zero replacement pattern detection circuit 4 and clears the first and second shift registers 8.9. The transmitted code a can be restored by the final stage output of the first shift register 8. The output of the final stage of the second shift register 9 can be used to detect errors.

FIG. 8 is a block diagram showing an embodiment when the value of the BnZS code On is 8, and FIG. 4 is a time chart showing signals of each main part to explain the operation of the embodiment. In this case, the first shift register 8 is an 8-stage shift register, and the second shift register 9 is an 8-stage shift register.
It is a stage shift register. Then, in the same manner as described with reference to FIG. 2, the conversion circuit 1 separates the input signal into the first pulse train d and the second pulse train d and outputs them. Assume now that the transmission code a is as shown in FIG. 4(a).

, that is, the transmission code a is ・110000000001
0011...'' and Toi is encoded with B8ZS, as shown in Fig. 5(e). In other words, a positive pulse is output in response to the first '1' of the transmission code a. ,
A negative pulse is output in response to the next "1". subsequent 8
+1.0.O, +1.- corresponding to two consecutive @0”
1. O, O.

-i is output. In other words, the zero substitution pattern is a bipolar pulse with the opposite polarity to the previous pulse, and when the bipolar erroneous pulse with the same polarity as the previous pulse is V, "B"
OOVBOOV'. Furthermore, subsequent 010011・
For ..., a normal bipolar pulse is output.

The above-mentioned zero substitution pattern "BOOVBOOV" can be detected by the combination of the position of the bipolar error pulse and the code butter y that corresponds to ``1'' to the bipolar pulse B and the polar error pulse V, respectively. and,
The received input signal C is a pulse sequence shown in FIG. In response to the received input signal C, a timing extraction circuit (not shown) outputs a timing signal as shown in FIG. Since the received input signal C does not include eight or more consecutive @O'', the timing can be easily extracted.

On the other hand, the first pulse train d output from the conversion circuit l is
Figure (d) shows the power supply line K, and the second path line is as shown in figure (-). Therefore, the output signal f of the OR circuit 7 becomes as shown in FIG. The signal f is input to the first shift register 8, and the shift register 8 performs a left operation on the input signal every time the timing No. 16 rises. Therefore, the output terminals Q1-Q of the first shift register 8.

The output states of each are as shown in FIG. 4, 11-i. Then, at the rising edge of the 9i-th timing signal, the states of the output terminals Q, ~Q, of the shift register 8 are respectively 1.1.0.0.1.1. O, O (Fig. 4 (1)
)~(11)), on the other hand, the first (D HA Jl/
The second pulse train d and the second pulse train e are detected by the bipolar error detection circuit 6, and the #j4 detection signal line 4 outputted from the error detection circuit 6 becomes as shown in FIG. 4(g). vA detection No. 16 g is an 8-stage shift register 9
The shift operation performed by V is performed by inputting a signal obtained by inverting the output signal f of the OR circuit 7 by an inverter to the clock terminal CLK of the shift register 9. Therefore, the first error detection signal g sets the output signal h1 of the output terminal Qt of the shift register 9 to @1m at the falling edge of the output signal f (see FIG. 4 (h,)).
. At the next fall of the output signal f, the output terminal Q*K@1" of the shift register 90 is set, and the terminal Q1 becomes 0" as shown in FIG. This state is 2
This continues until just before the th erroneous detection signal g is output and falls. Then, the second false detection signal g sets the output h1 of the register 90 to "1" by the fall of the output signal fO of the OR circuit 7.
”, then output btu “O”, output is @1
''. Also, when the 10th timing signal rises, the output of the first stage of the first register 8 becomes @1'', and the second
~8th stage output 1m~1- are respectively 0.0, 1, 1,
0,0,1 is dangerous. At this moment, the output of the nine-zero replacement pattern detection circuit 4 constituted by the AND circuit of the Kll input becomes high level, and the first and second registers $ and 9
is cleared. That is, the contents of all registers are cleared at the rising edge of the 1G-th timing pulse.The above operation is instantaneously performed at the rising edge of the 10411-th timing pulse, and from then on, the contents of the l-th register 8 are cleared. Eight consecutive "0's" are output from the output, and only the instantaneous 11" is output from the final stage of the second register 9.

The above-mentioned instantaneous "1" is ignored as a bipolar 2 error detection signal. Each input of the AND circuit 4 is connected to the first and second inputs.
It is possible to detect a zero substitution pattern by connecting the outputs of each stage of the shift registers 8 and 9 or their negative outputs in a manner corresponding to some patterns. After the zero substitution pattern is detected, eight consecutive "0" codes are output, and after that, codes corresponding to the input signal are output.

If there is a bipolar error in a general code other than the zero replacement pattern, the error can be detected by the final stage output of the second shift register 9. Therefore, when an erroneous signal is mixed in due to noise in the transmission path, the code WAJ) can be detected by detecting the bipolar erroneous signal. In the above embodiment, the first shift register 8 is an 8-stage shift register. Since the second shift register 9 is an eight-stage shift register, there is an effect that the scale of the shift register can be smaller than that of the nine conventional example shown in FIG. In addition, in conjunction with this, the zero replacement pattern detection circuit 4 runs out when comparing 11-bit patterns. Further, there is no need to detect two types of zero substitution patterns with different polarities as in the conventional method. That is, there is an effect that the overall circuit scale can be made smaller than the conventional one.

As described above, in the present invention, the first pulse train corresponding to the positive polarity pulse of the received input signal and the 20th pulse train corresponding to the negative polarity pulse are separated and outputted, and the first and second pulse trains are outputted separately. are combined by an OR circuit and input to the first shift register, and the output state of the bibolar large detection circuit that detects /(Ibonira v74e) is stored in the second shift register from the first and second pulse trains. By comparing the states of the outputs of each stage of the first and second shift registers with a partial pattern, a zero substitution pattern is detected. Since the structure is configured to clear the second shift register, there is an effect that the scale of the shift register and zero substitution pattern detection circuit can be made smaller than that of the conventional example.

[Brief explanation of drawings]

FIG. 1 is a block diagram including a partial logic diagram showing an example of a conventional BnZS decoding and error p detector; FIG. 2 is a block diagram including a partial logic diagram showing an embodiment of the present invention; FIG. 4 is a block diagram including a partial logic diagram showing an embodiment in which the present invention is applied to the B8ZS signal, and FIG. 4 is a time chart showing various signals for explaining the operation of the embodiment shown in FIG. 8. . In the figure, 1... conversion circuit, 2... shift register, 8... shift register of ship 1, 4.5... zero substitution pattern detection circuit, 6... bipolar error detection circuit, 7. 8... OR circuit, 9... Second shift register. Agent: Patent attorney Toshimune Sumita

Claims (1)

[Claims] B! A conversion circuit that separates the received signals of 12811 into positive polarity pulses and negative polarity pulses and outputs the first and second pulse trains, and a 9-piport WA where pulses of the same polarity are continuous.
and a bipolar erroneous ray detection circuit for detecting bipolar erroneous rays, and when the first and the meI Bm outputs the decoded output with the code changed to “O” code.
In the Z8 decoding and error detector, the first and second ! An OR circuit that inputs the O pulse train, an nfRO first shift register that inputs the output of the OR circuit, and inputs the first and 20th pulse trains output from the front ffi envy circuit, so that the first and 20th pulse trains alternate. a bipolar error detection circuit which outputs a detection signal when input to tk, a second shift register to store the output state of the output signal O of the f-ram detection circuit; a zero substitution pattern detector which inputs the outputs of each stage of the second shift register and the output of each stage of the first shift register and clears the first and second shift registers when both inputs have a constant pattern; and said first
1. A BnZS decoding and false shift detector, characterized in that the final stage output of the 0 shift register is used as the decoding output, and a bipolar false shift detection signal is obtained from the final stage output of the 20th shift register.