JPS5877312A - Magnification circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention generally relates to an analog signal multiplier or signal gain control system, and more particularly, to an analog signal multiplier or signal gain control system, and more particularly, to an analog signal multiplier or signal gain control system, and more particularly to an analog signal multiplier or signal gain control system. This invention relates to a voltage controlled amplifier provided with rounding compensation to correct for.

Many systems, particularly audio or video signal processing systems, have signal gain control circuits that are controlled in response to electrical command or control signals. A commercially successful signal gain control circuit was developed by DBX, Xna, a Massachusetts company.

Javii Ilf, January 30, 1973, licensed and manufactured by K.

U.S. Patent No. 3,714,4 awarded to BlaOkmer
No. 62 Kf! It has a magnification circuit of a controlled and proprietary type. Below, the above circuits are collectively DB! It is called a magnification circuit. DB! A multiplier circuit generally includes means for providing a first signal that is a logarithmic function of the circuit's input signal;
and means for algebraically adding a control signal to the signal.

The level of signal gain is a function of the control signal. DB! The multiplier circuit also has means for providing an outlay that is an antilogarithmic function of the algebraic sum of the first signal and the control signal. DB! The multiplier circuit can be bipolar, ie the input signal can be of positive polarity and/or negative polarity i. DB! The gain provided by the multiplier circuit can be amplification or attenuation.

Favorable DB! The magnification circuit has an operational amplifier and an amplifier. Each gain unit has a logarithmic-linear pace factor i.
It has at least two transistors exhibiting voltage/collector current (vb/Za) conversion characteristics. These two transistors are each connected to the amplifier by a conductive feedback path of opposite polarity. These two transistors provide logarithmic signals in response to positive and negative input signals, respectively. The gain device also has at least two further transistors which also exhibit a log-linear (113a/C) variable characteristic and are each connected to the two aforementioned logarithmic signal conversion transistors.

These two other transistors each provide an output signal as an anti-logarithmic function of the algebraic sum of the control signal and the logarithmic signal. The gain of these transistors can preferably be controlled by a control voltage applied to a selected one of the transistors.

The preferred gain of the DB1 multiplier circuit uses at least two ppP conduction type transistors for one polarity of the input signal and at least two NPli
Conducting type transistors are used for input signals of opposite polarity.

I) Certain types of BX multiplier circuits have had the problem that certain errors occur with relatively fast changes in the control signal. Parable d.

If the operational amplifier of the DBX multiplier circuit is of the type that generates a voltage output, then the gain
With rounding being connected, a sudden increase in the control voltage applied to the gain produces a sudden increase in the voltage at the output level of the operational amplifier. Because a portion of the gain amplifier forms the amplifier's feedback path, and because all amplifiers have a finite voltage gain, a sudden increase in the output voltage level of the amplifier
This in turn causes an increase in the input voltage level of the amplifier. An impedance provided at the input of the amplifier discharges this erroneous signal. However, the discharge of the error signal is usually too slow;
Generates an error current signal at the input of the amplifier.

The error signal is amplified by a gain and generates an error output current signal for the circuit. In audio applications, this error output current signal generates sanding noise.

One object of the present invention is to provide an improved magnification circuit that reduces and substantially eliminates the above-mentioned problems of the prior art.

Another object of the invention is to provide an improved multiplier circuit that provides compensation for errors that occur in response to rapid changes in control signal level.

It is another object of the present invention to provide an input operational amplifier and a method for substantially reducing or eliminating error signals often generated by the amplifier and amplified by the gain control signal in response to changes in the level of the gain control signal. It is an object of the present invention to provide an improved multiplier circuit of the type having a gain device that can be used.

These and other objectives are achieved by an improved multiplier circuit of the type having an input operational amplifier and a gain unit. The gain device is configured such that the first signal can be generated as a logarithmic function of the input signal in response to the input signal, and the control signal can be added algebraically to the first signal.
The second signal is coupled to the input operational amplifier such that the second signal can be generated as a function of an algebraic sum of the first signal and the control signal.

An improvement consists in having means for producing a correction signal at the output of the input operational amplifier. The correction signal is a function of the control signal level and has substantially equal absolute value and opposite sign (opposite polarity) to the signal produced by relatively fast changes in the control signal at the output of the operational amplifier.

The present invention will be explained below based on illustrated embodiments.

FIG. 1 is a schematic circuit diagram of a magnification circuit according to a first embodiment of the present invention.

The circuit shown in FIG. 1 is a typical multiplication circuit to which this embodiment can be applied.

The magnification circuit has a ninth input terminal 100 which receives an input current signal 1n of either positive or negative polarity or one polarity. Input current line 1n receives input voltage Vin from voltage source 102 (e.g., an audio signal source or a video signal source).
The voltage applied through the input f-dance load 104 is generated.

The input terminal 100 #i is connected to the inverting input terminal of the input operational amplifier 106 . The non-inverting input terminal of input operational amplifier 106 is grounded. In general, the amplifier 106 is of a type with a certain finite output admittance or of a type with a Kg resistor 108 connected at the output terminal. The output terminal of amplifier 106 is connected to the inverting input terminal via two feedback paths.

Each feedback path has a gain 1100 with eight transistors and a pace-emitter connection of two logarithmic transistors. More specifically, the output terminal of the amplifier 106 is connected to a resistor 112 via a resistor 108;
12 is connected to the collector of the gain 11GONPM logarithmic transistor 114. The output of the logarithmic transistor 114 is the PMP logarithmic transistor 1 of the gain unit 110.
Connected to 16oz-i ivy. transistor 11
The collector of No. 6 is connected to the input terminal IQOK'M so that a first feedback path is formed. Similarly, amplifier 106
The output terminal of is connected to a voltage bias source 146 via a resistor 108, and the voltage bias source 146 is connected to a resistor 118. Resistor 118 is connected to the collector of gain section 1100PNp logarithmic transistor 120. The two terminals of the logarithmic transistor 12G are connected to the terminal Km of the logarithmic transistor 122 of the gain section 1100MPM. The collector of logarithmic transistor 122 is connected to the input terminal, child 100, to form a second feedback path.

The gain unit 110 has anti-log signal conversion means for each polarity of the input signal. The connection point between resistor 108 and resistor 112 is connected to resistor 124. A resistor 124 is connected to the collector of a gain 1100 MPH antilogarithm transistor 126.

The output of the anti-logarithm transistor 121 is the gain unit 1100.
It is connected to the output terminal of the PIP antilogarithm transistor 128. The collector of antilog transistor 128 is connected to the output terminal 130 of the circuit. Similarly, the junction between bias source 146 and mK 118 is connected through a resistor 132 to the collector of gain 1100PliP antilogarithm transistor 134. The emitter of antilogarithm transistor 134 is connected to the output of an NPli antilogarithm transistor 136 of gain unit 110. transistor 1
The collector of 36 is connected to the output terminal 130.

The pace and collector of logarithm transistor 1140 are coupled to the collector and pace, respectively, of antilogarithm transistor 126. Similarly, transistor 1200 pace and collector are coupled to the collector and pace of antilog transistor 134, respectively. The pace of logarithmic transistor 116 is grounded. On the other hand, anti-logarithm transistor 1
36 is grounded via a resistor 138. Logarithmic transistors 114 and 116, resistors 112 and 124, and antilogarithmic transistors 126 and 128 form a first signal processing circuit for one polarity of the input signal. On the other hand, logarithmic transistors 120 and 122, resistors 118 and 132, and antilogarithmic transistors 134 and 136 form a second signal processing circuit for the other polarity of the input signal.

The paces of transistors 122 and 128 are connected together and to a control signal (1!fc) input terminal 140. One transistor 114°116.1
26.128 and the other transistor 120, 122
, 134 and 136, the pigeon loft has a
Gain matching is obtained by adjusting an adjustment potentiometer 142 (suitably biased to a voltage source) connected through a resistor 144 to the pace of resistor 136.

The gain device 110 is connected between the connection point provided between the resistors 118 and 132 and the connection point provided between the resistors 112 and 124! It is suitably biased by a bias voltage source 146 connected to the circuit. The bias voltage source 146 may be a DC battery or alternatively a voltage source such as that described in US Patent Application No. 247,648, filed March 26, 1981. A constant current source is connected to the connection point between the resistors 118 and 132 of the gain device 110. Preferably, the connection point between the ridge resistors 118 and 132 is MPli) transistor 148. connected to the collector. The emitter of transistor 148 is connected to constant current source 150.

The base of transistor 148 is connected to ground through six voltage drop diodes.

To the extent described thus far, U.S. Pat.
, 462 and U.S. Patent Application No. 24-648.

An input signal is applied to the input terminal 100, and a control signal E0 is applied to the control signal input terminal 140. For a negative input signal at input terminal 100, the %eL upper half signal processing circuit becomes conductive and transistor 114
and 116 generate a voltage signal as a logarithmic function of the input current signal.

A terminal 1400 control signal is applied to the transistor 128 pace. Inverse-log transistors 126 and 128 subsequently provide an output current signal to output terminal 13G.

This signal is an antilogarithmic function of the sum of the control signal and the logarithmic signal.

Similarly, for a positive input signal at input terminal 100, the lower half of gain 110 becomes conductive. Transistors 120 and 122 generate a logarithmic voltage signal as a logarithmic function of the input current signal. The control signal is added to the pace of transistor 122, which is algebraically added to the aforementioned logarithmic voltage signal. Anti-log transistors 134 and 136 generate an output current signal as an anti-log function of the algebraic sum of the log signal and the control signal.

During operation, the multiplier circuit operates in a preferred manner when the control signal level remains substantially unchanged or varies gradually. However, at least in audio applications, sudden changes in the level of the control signal that result in rapid changes in gain generate syf song noise. The inventors have discovered that sampling noise is caused by rapid changes in the voltage at the output of amplifier 106 in response to fast changes in the control signal. This fast change in the output voltage level of amplifier 106 produces a fast change at the inverting input of amplifier 106. This input voltage error is
It appears across the input impedance 104Yt and is processed as part of the input and current signal circuit 1n, thus causing an error.

This problem can be illustrated by the following example. If a sudden change occurs in the terminal 1400 control signal (e.g., from 0 to -240 mV resulting in a gain of 100), a voltage of half magnitude (-12'OmV) is applied to the junction of resistors 112 and 124. Change occurs. Current source 1
50 and bias voltage source 146 when there is no input signal.
A friend, resistor 1, is supplied with a constant current through resistor 108.
A voltage change at the junction of 12 and 124 produces an equal change on the opposite side of resistor 108 at the output of amplifier 106.

A voltage change at the output of amplifier 106 provides a voltage change at the inverting input of amplifier 1060. This error voltage at the inverting input of amplifier 1060 is due to the input impedance of the circuit 104t-
After that, an error current is generated.

Gainer 110 amplifies the error current no matter what gain it is set to and generates an error signal at output terminal 130. Eventually, the error voltage at the input terminal 100 of the amplifier 106 is discharged through an RO circuit (not shown) typically provided at the input of the amplifier 106.

However, such a discharge cannot prevent the initial amplification of the error signal.

According to the invention, in order to substantially cancel out the change in voltage at the junction of the resistor 108 and the output of the amplifier 106 that would otherwise occur in response to a sudden change in the control signal level at the terminal 140. means are provided. In this embodiment, canceling the voltage change at the junction of the resistor 108 and the output of the amplifier 106 is achieved by canceling the voltage drop across the resistor 108 that is equal in absolute value and of opposite sign to the voltage change caused by the change in control signal level. This is achieved by simultaneously generating and flowing a current generated by sandwiching the resistor 108 through the resistor 108.

Ru.

More specifically, if the change in the control voltage signal at terminal 140 is
When c K is equal, the voltage change at the connection point of resistor 112 and resistor 124 is l1i6/2. In order to generate a cancellation correction voltage across the resistor 108, "c/(2・R1
08) An additional correction current equal to K must be generated to flow through resistor 108. Here, R108 is the resistance value of the resistor 108.

Referring to FIG. 1, this additional correction current “O/(2・
R108) is H between the constant current source 150 and the terminal 140,
This can be easily provided by connecting a correction resistor 200 with a resistance value equal to twice the resistance value of R108. When a change occurs in the voltage IC at terminal 140, resistor 20
0 through which an additional correction current equal to 10/(2·1108)K is generated.

In response to this current, an equal current is generated through resistor 10B to provide the necessary correction. resistance.

By generating the necessary correction current through 108, the error voltage is canceled out.

FIG. 2 shows a second embodiment of the invention.

As shown in FIG. 2, a correction resistor of 200 μm can be connected between the junction of resistors 112 and 124 and terminal 140. The voltage change at the connection point of resistors 112 and 124 is “o/
Since 2 K is equal, the additional current required for the current flowing through the resistor 108 is ``O/(2・R200 μm).
In this case, R200m is the resistance value of the resistor 200m, which is necessarily equal to Ku108. According to the present invention, a correction voltage can be applied to the output of the amplifier 106. As long as the amplifier 106 generates an output voltage in response to some input (voltage or current), it requires a change in the current flowing through a finite impedance or resistance to maintain the voltage output constant; resistance 1
It must have an output impedance or resistance of some finite value, such as .08.

This invention can be applied to different gain devices such as U.S. Pat.
Other multiplier circuits with four transistor gainers, such as that shown in US Pat. No. 4,462, are also applicable.

Note that this invention can be modified in various ways without departing from the spirit of the claims, and the above description of the actual implementation is not intended to limit or limit this invention.

[Brief explanation of drawings]

FIG. 1 is a schematic circuit diagram of a magnification circuit according to a 11j embodiment of the present invention, and FIG. 2 is a schematic circuit diagram of a magnification circuit according to a second embodiment of Jin's invention. 10°0...Input terminal, 102...Voltage source, 10
4... Input impedance load, 106... Input operational amplifier, 108... Resistor, 110... Gain unit,
112-...Resistor, 114...IIIPN logarithmic transistor, 116...PNP logarithmic transistor, 11
8...Resistor, 120...PNP logarithmic transistor,
122...NPN logarithm transistor, 124...Resistor, 126...NPM antilogarithm transistor, 128...
...PNP antilogarithm transistor, 130...output terminal, 132-...resistance, 134...PNP antilogarithm transistor, 136...MPM antilogarithm transistor, 1
38...Resistor, 140...Control signal input terminal,
142... Potentiometer, 144... Resistor,
148...Bias voltage source, 148...ypi) transistor, 15o...constant voltage source, 200.200m...correction resistor. Agent Akira Asamura 4 people FIG, / FIG, 2

Claims (7)

[Claims] (1) means having an input amplifier and a gain device coupled to the output of the input amplifier, the gain device responsive to the input signal generating a first signal as a logarithmic function of the input signal; and a control signal as a function of the gain of the circuit.
a multiplier circuit comprising: means for algebraically adding to a signal; and means for generating a second signal as an antilogarithmic function of an algebraic sum of the first signal and the control signal; - means for applying a correction signal to the output of the input amplifier as a function of the control signal, the correction signal being substantially equal in absolute value and having an opposite sign to the signal generated at the output of the input amplifier; A magnification circuit d characterized by (2) In the magnification port W& according to claim 1, the input amplifier generates a voltage signal at its output in response to the input signal, and the means for providing the correction signal includes the control signal A multiplier circuit characterized in that it comprises means for applying a correction voltage to the output of said input amplifier equal to half the change in . (3) The multiplier circuit according to claim 2, further comprising a first impedance means provided at the output end of the input amplifier, and the means for providing the correction signal is configured to provide the first impedance means. A multiplier circuit comprising means for generating a correction current flowing through said first impedance means in response to said control signal so as to generate a correction voltage therebetween. (4) A multiplier circuit according to claim 3, including a control signal input terminal for receiving the control signal as a voltage signal, and a substantially constant current for supplying a bias current flowing through the gain device. and the means for generating a correction current has a second impedance means coupled between the control signal input terminal and the means for generating a substantially constant current. A magnification circuit characterized by: (5) In the magnification circuit according to claim 4,
The first impedance means has a first resistor provided at the output end of the input amplifier, and the second impedance means has a second resistor having a resistance twice that of the first resistor. A magnification circuit characterized by: (6) In the magnification circuit according to claim 3,
The means for generating the correction current has a control signal input terminal for receiving the control signal as a voltage signal;
A multiplier circuit comprising a second impedance means coupled between the control signal input terminal and the first impedance means. (7) In the magnification circuit according to claim 6,
The 11i1 impedance means has a first resistor provided at the output end of the input amplifier, and the second impedance means has a second resistor having the same resistance value as the first resistor. magnification circuit.