JPS587871A - Diode and its manufacturing method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductors, particularly amorphous silicon, and relates to 4j5. The purpose is to improve the reliability of %O8) transistors and MOS) transistor circuits by providing diodes that protect the inputs of MOS) transistors.

A MOS transistor has an insulating gate oxide film or an insulating film, and therefore charges are easily stored in the gate insulating film. For this reason, it is known that they can be easily destroyed by static electricity or surge-like overvoltage. To prevent this, for example, in the case of an n-channel MOS transistor, a protection diode 105 is placed between the gate 101 and the silicon substrate 104 as shown in FIG. 1a. gate 1o1
When a positive overvoltage is applied to the substrate 104, the diode 105 breaks down in the reverse direction, and when a negative overvoltage is applied, the diode 105 acts in the forward direction, causing current to flow and reduce the voltage of the diode 105, that is, the gate insulating film. The voltage is clamped to protect the gate insulating film.

MOS) transistor on an insulating substrate, e.g. 503-M
2S) Since a silicon substrate is not present in a transistor, a protection diode 105 is generally placed between a gate 1o1 and a source 103 as shown in FIG. Note that in the case of a p-channel, the polarity of the protection diode may be reversed.

Amorphous silicon, which contains several atoms or less of hydrogen in its composition to compensate for imperfections in atomic bonds, has a low cost because it can be easily made into a large area and can be manufactured at low temperatures. In addition to cost-effective solar cells, various application developments have been proposed. However, compared to single crystal silicon, amorphous silicon has a high local level density and extremely low free carrier mobility, making it difficult to obtain a MOS transistor with large mutual conductance.

However, it is not necessary to flow a large amount of current, and high-speed operation is not required. For example, in MO3) transistors for switches used in combination with liquid crystals to construct an image display device, a slight improvement in performance over the current state is sufficient. The present inventor has already developed amorphous silicon M by providing a thin and pinhole-free gate insulating film.
O3) It was revealed that the performance index of transistors has been improved.

It has been found that the gate insulating film of an amorphous silicon MO3) transistor formed on an insulating substrate such as a glass plate is extremely susceptible to destruction, as in the case of SO8. This seems to be because not only the gate insulating film but also the insulating substrate is charged. Therefore, a diode for protecting the gate is essential even in an amorphous silicon MOS transistor.

However, currently reported amorphous silicon M
O8) A transistor does not have a built-in gate protection diode because the gate insulating film is thick and it must be handled carefully at the laboratory level. In other words, there are no prior examples to cite.

When obtaining a diode using amorphous silicon, the second
It goes without saying that either the junction diode shown in Figure a or the Schottky diode shown in Figure 2 is easy. The junction diode has a configuration in which a three-layer pin amorphous silicon layer 2o1 is sandwiched between metal electrodes 202 and 203, and the reverse breakdown voltage is controlled by changing the thickness of the i-layer or adding a small amount of impurity to the i-layer. It is possible. In a Schottky diode, a layer 205 consisting of an amorphous silicon layer 205a containing a large amount of n-type impurities, such as phosphorus or arsenic, and an amorphous silicon layer 205b containing almost no impurities, is connected to a cando metal electrode 206 and an anode metal electrode 207. A sandwiched structure is adopted, and the reverse breakdown voltage can be controlled by changing the thickness of one layer 2o5b or by adding a small amount of n-type impurity to the i-layer.

1 is an insulating substrate such as a glass plate, and 204 is a metal electrode 20.
3 and the amorphous silicon layer 201, but since amorphous silicon generally has a high resistivity, it may be unnecessary in some cases.

In order to manufacture an amorphous silicon diode, three to four mask steps are required as shown in FIG. In addition, 3 to 4 mask processes are also required to fabricate an amorphous silicon MO8) transistor, but the number of process steps will inevitably increase if a MOS transistor with a built-in protection diode is fabricated. For example, three pin layers are required for a junction diode, and only an i layer is required for a MOS transistor. In this case, the amorphous silicon will need to be deposited more than once, and an etching process will also be required to separate and arrange the pin and i-layer islands. Since an increase in the number of steps inevitably results in an increase in cost and a decrease in yield, it is extremely important to obtain a MOS transistor with a built-in protection diode while preventing an increase in the number of steps. In addition, as the number of times amorphous silicon is deposited increases, the film quality often deteriorates due to the heat during deposition, and care must be taken to avoid this.

The present invention has been made in view of the above-mentioned problems, and the number of mask steps is only increased by two, and it is possible to incorporate a protection diode with a large protection ability. It is also very effective in the case of OMO8, and the key point is the Schottky diode of vertical structure, and embodiments of the present invention will be described with reference to the drawings from FIG. 3 onwards.

First, as shown in FIG. 3a, a first amorphous silicon layer 2 containing a large amount of n-type impurities, such as phosphorus, is selectively deposited on an insulating substrate, such as a glass plate 1. For reasons described later, it is desirable that the film thickness is thicker, for example, 20oO to 5oO
Chosen by Oo people.

Then, as shown in FIG. 3, a second amorphous silicon layer 3 is selectively deposited so that the first amorphous silicon layer 2 is not completely hidden. The thickness of the second amorphous silicon layer 3 may be 1000 Å or more, for example, 4000 Å or more.
It is selected by humans and does not require the addition of impurities. In forming the second amorphous silicon layer 3, the first
In order to prevent the first amorphous silicon layer 2 from disappearing, the first amorphous silicon layer 2 must be thick to some extent. A71 continues to cover the entire surface! The first metal layer 4 consists of a film thickness of 2
It is applied with o○. Further, as shown in FIG. 3C, a silicon nitride film 6 is formed on the first and second amorphous silicon layers.
is selectively deposited. The first metal layer 4 and the metal electrode 6 are connected around the substrate 1, and a positive bias is applied to the region where oxygen plasma is generated to perform plasma anodic oxidation.

The oxidation conditions were 0 pressure, 1 Torr, and 7×300V.
, the substrate temperature is 300°C. After about one hour, the first metal layer not covered with silicon nitride film 5 becomes metal oxide.

The first metal layer 4 is made of, for example, Al whose oxide serves as an insulator, so the oxide is made of alumina (A
l2o3) Ryo is formed and the film thickness increases to 400 people. After plasma anodization, the silicon nitride film 6 is removed as shown in FIG. 3d, and the first metal layer made of Al under the silicon nitride film 5 is also removed to form the first and second amorphous Silicon layer 2.3 is partially exposed. Then, as shown in FIG. 3e, a second metal, such as PT, is selectively deposited on the exposed first and second amorphous silicon layers to form a diode according to the present invention. Complete. The first amorphous silicon layer 2 containing a large amount of phosphorus forms an ohmic electrode with the second metal layer 8, and the second amorphous silicon layer 3 containing almost no impurities forms an ohmic electrode made of a second metal. Since it is in contact with the electrode 9, it can be seen that a Schottky diode having almost the same structure as shown in FIG. 2 is constructed.

FIG. 4 shows a cross-sectional view of the process of manufacturing a MOS transistor, which is carried out simultaneously with the fabrication of a diode according to the present invention, and FIG.
Naturally, the steps corresponding to are omitted, and the same steps as in FIG. 3 1)-e are carried out in the cross-sectional views of FIGS. 4a-d. M.O.S.
) In the case of a transistor, an alumina film γ' formed on the island-shaped second amorphous silicon layer 3 constitutes a gate insulating film. Furthermore, in the step of FIG. 4C, unlike the case of FIG. 3D, after providing an opening in the silicon nitride film 6, the first
0 Metal layer 11.12 must not be removed. For this reason, the first
It is necessary to cover the metal layers 11 and 12 with a photosensitive resin. The first source drain/wiring is made of Al.
metal layer 11.12 or a second metal layer 13.14 made of PT 3 via them. Since amorphous silicon, which contains almost no impurities, and Al form a relatively good ohmic contact, the MOS transistor shown in FIG. 4 is characterized in that it can operate in both channels. In the case of an n-channel, the cathode 8 is connected to the gate 16 and the anode 9 is connected to the source 13, and in the case of a p-channel, the cathode and anode are reversely connected.

As mentioned above, although the deposition process of the amorphous silicon layer containing n-type impurities is increased by one time and the mask process is increased by two times, the protection diode is In contrast, the present invention provides a diode with a high current density per unit area, that is, a high protection ability.In contrast to a diode, in which the effective junction area cannot be increased because the diode current flows parallel to the semiconductor layer, the present invention provides a diode with a high current density per unit area, that is, a diode with a high protection ability. Amorphous silicon MO8), which has the same protection ability as silicon, means that a transistor circuit can be fabricated on an insulating substrate, and does not compensate for the drawback of low carrier mobility by making the gate insulating film thinner. This also meets the objective of promoting the integration of transistors into integrated circuits. As already mentioned, it is also an effective protection diode for amorphous silicon MO8 transistor circuits.

The method of depositing the amorphous silicon layer is glow discharge, sputtering,
It goes without saying that any CvD method may be used, and the present invention is also applicable even if amorphous silicon is partially crystallized by hydrogen plasma annealing or laser annealing. The metal wiring electrodes that form the Schottky barrier include Ir, in addition to PT.

Many metal materials such as Pd and Rh can be used.

[Brief explanation of the drawing]

Equivalent circuit diagrams showing the relationship between odes, Figures 2a and b are cross-sectional views of diodes made of amorphous silicon, Figure 3a,
b, c, d, and e show process cross-sectional views of the Schocke diode according to the present invention, and Fig. 4 a, b. c and d show process cross-sectional views of an M03) transistor obtained simultaneously with the fabrication of the diode according to the present invention. DESCRIPTION OF SYMBOLS 1...Insulating substrate, 2...Amorphous silicon layer containing n-type impurities, 3...Amorphous silicon layer, 4......No. 1 metal layer, 6...silicon nitride film, 6...metal electrode, 7'...
...Metal oxide film, 8...Cathode electrode, 9
...Anode electrode, 11, 13, 12゜14...Source/drain electrode, 15...
...Gate electrode, 1a5...Protection diode,
2o1...pin three-layer amorphous silicon layer,
205a...Amorphous silicon layer containing n-type impurities, 2o6b...Amorphous silicon/layer containing almost no impurities. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 α61 @3rA 2 113 Figure II 4 Figure @ 4 m

Claims (1)

[Claims] (1) A first non-single crystal silicon layer containing n-type impurities is selectively deposited on an insulating substrate, and a second non-single crystal silicon layer partially containing the first non-single crystal silicon layer is formed. A silicon layer is selectively deposited, and a metal oxide film having an opening is deposited over the first and second non-monocrystalline silicon layers, with the first non-monocrystalline silicon layer serving as a cathode. Further, a diode characterized in that a metal wiring serving as an anode is selectively deposited on the second non-single crystal silicon layer. @) A step of selectively depositing a first non-single crystal silicon layer containing an n-type impurity on an insulating substrate, and forming a second non-single crystal silicon layer partially containing the first non-single crystal silicon layer. A step of selectively depositing a crystalline silicon layer, and a step of selectively depositing a silicon nitride film on the first and second non-single crystal silicon layers after depositing a first metal layer on the entire surface. and selectively converting the first metal layer into a metal oxide film by plasma anodization, the first and second non-monocrystalline silicon layers exposed after removing the silicon nitride film and the first metal layer. A method of manufacturing a diode, comprising selectively depositing a second metal layer thereon.