JPS5879385A - Television receiver - Google Patents

Abstract

PURPOSE:To picture of 9 or 4-channel picture at the same time, by using a few number of tuners, through the use of a 9-notation ring counter and a 4-notation ring counter and the sequential channel selection of a plurality of channels at a prescribed period. CONSTITUTION:In operating a mode changeover switch 27 to the 9-screen mode, a clock pulse is applied to a 9-notation ring counter 19 and an address counter 22, and the output of the counters 19 and 22 is sequentially switched. As a result, the tuning voltage of a channel selection circuit 14 is sequentially switched and applied to a tuner 2, and nine channels are sequentially and repetitively selected received. In this case, a video signal obtained sequentially from a video detection circuit 4 is applied to a storage device 24. The write and readout positions are designated with the counter 22 at the device 24. The video signal of each channel is sequentially and repetitively read out in the order designated at the counter 22. The similar operation can be done in operating the switch 27 to a 4- screen mode. Thus, nine or four pictures can simultaneously be pictured on the screen of a cathode ray tube 7.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a television receiver that can simultaneously display images of a plurality of channels on one screen.

Conventionally, this type of television receiver was manufactured by a patent application issued in 1972.
39273 (Japanese Unexamined Patent Publication No. 49-2419) etc., a system that simultaneously displays images of two channels, a main channel and a sub channel, on one screen has already been proposed and partially put into practical use.

However, such a television receiver can display only two images at the same time, and if more images are to be displayed simultaneously, it is necessary to install an additional tuner for the number of images.

Currently, in Japan, the number of broadcast stations that can be received in one area is nine channels at most, and if nine images are displayed simultaneously on one screen, it is possible to check all broadcast channels in that area at the same time. In this case, normally 9 chips and 9 storage devices such as BBD or RAM are required.

The present invention provides a television receiver that can simultaneously display images of nine channels or four channels on one screen using fewer tuners than the number of images to be displayed.

The present invention will be described below according to embodiments shown in the drawings. 1st
The figure is a block diagram showing one embodiment of the present invention. Here, as shown in FIGS. 2 and 3, one cathode ray tube screen is divided into nine parts kA, B, C, and , to,
It is divided into four parts, L and M, and images of nine or four channels are displayed simultaneously.

In Fig. 1, 1 is an antenna, 2 is a tuner, 3 is a video intermediate frequency amplification circuit, 4 is a video detection circuit, 5 is a video amplification circuit, 6 is a video output circuit, 7 is a cathode ray tube, 8 is an audio detection circuit, and 9 is a video output circuit. 10 is a speaker, 11 is a synchronous separation circuit, 12 is a horizontal deflection circuit, 13 is a vertical deflection circuit, and 14 is a switching transistor TRI, T.
R2, TR8, . . . TR, channel setting variable resistors VR, VB2, VH2 ---VB2, and automatic tuning circuits D1, D2, D3, . . . D, and 15 is also the switching transistor TR5
o, TRs+...TR, 5, channel setting variable resistor VR+o-VR+.

. . . A second channel selection circuit consisting of DI.

In this embodiment, a television receiver comprising the above components further includes a clock pulse generator 16, an electronic switching circuit 17, 18, a 9-ary ring counter 19, a 4-ary ring counter 20. Signal switching circuit 21, address counter 22. An AD converter 23, a storage device 24, and a DA converter 26 are provided.

Here, in the clock pulse generator 16, approximately 200 m5
A clock pulse of ec is generated. If the mode changeover switch 27 is now operated to the 9-screen mode or the 4-screen mode, either the 9-ary ring counter 19 or the 4-ary ring counter 2o will be activated, and the electronic switching circuits 17 and 18 will be turned on. state and a clock pulse is applied to the ring counter 19 or 20.

Here, approximately 2
The clock pulse of 00mae (! is the switching circuit 1
7 to the 9-ary ring counter 19. At this time, the clock pulse is not supplied to the address counter 24 either, and the ring counter 19 and address counter 22 output their outputs at intervals of 200m5ec.
The switching transistor T
R and -TR are sequentially turned on at predetermined intervals (approximately 200 m5ec), and the tuning voltages set to each variable resistor VRI to vR are sequentially switched and supplied to the tuner 2. As a result, in tuner 2, variable resistors VR, ~VR
, are repeatedly selected and received in sequence every 1.8 seconds.

At this time, the video signals of each channel sequentially obtained from the video detection circuit 4 are once converted into digital information by the AD converter 23 and supplied to the storage device 24. Here, the storage device 24 is composed of a group of nine digital storage elements such as 1tAM, has a storage capacity for nine screens, and the address counter 22 specifies the write and read positions.

In the storage device 24, the digital video information of each channel is extracted at a rate of one every three scanning lines based on the control signal from the control signal generation circuit 26, and is stored in the storage element at the designated address for one frame (one screen). Written in minutes. Note that the address counter 22 is the above-mentioned 9-ary ring counter/
Since the video information of each channel is individually written to the same storage element because it is driven by clock pulses at the same time as the signal 19. In other words, the video information of each channel written in each storage element is intermittently rewritten every 1.8 seconds.

Meanwhile, in the storage device 24, the address counter 22 specifies the video information of each channel from each storage element at a higher speed than the writing speed (in this case, three times the writing speed) based on the control signal from the control signal generation circuit 26. They are read out sequentially and repeatedly in the same order.

The digital video information of each channel read out from the storage device 24 in this way is converted into an analog video signal by the DA converter 25, and then supplied to the cathode ray tube 7 via the signal switching circuit 21 and the video output circuit 6. As a result, nine channels of images are displayed simultaneously on the cathode ray tube screen as shown in FIG. In this case, each image is switched to a new image every 1.8 seconds, and remains a still image for 1.8 seconds during this time. The inventors have confirmed through experiments that with a still image of this level, it is possible to fully understand the broadcast contents of each channel, although the video may have some strobe-like movement. Of course, the clock pulse period of the clock pulse generator 16 is set to 150m5ec% or 100m5ec%.
Needless to say, the shorter the length, the more natural the image will be.

By switching the mode selector switch 27 to the 9-screen mode, nine channels of images are simultaneously displayed on the cathode ray tube screen as shown in FIG. Note that in this case, since the operation of the audio amplifying circuit 9 is stopped, no audio is emitted from the speaker.

Next, a case will be described in which four screens are projected on a cathode ray tube screen. In this case, first set the mode selector switch 27 to 4.
When switching to the screen mode, the electronic switching circuit 18 is turned on and a clock pulse is applied to the quaternary ring counter 20. At this time, the other electronic switching circuit 17 is turned off.

Note that the 4-screen display operation in this case is performed in almost the same way as the 9-screen display operation described above, but when the video information is stored in the storage device 24, the scanning line is One out of every two lines is extracted, and one frame (one screen)'s worth is written into the memory element at the specified address.

At this time, the images of the four channels are displayed on the cathode ray tube screen as shown in FIG. When switching to the screen mode or 4-screen mode, pictures of nine or four channels are displayed simultaneously on the cathode ray tube screen, and during this time, the sound from the speaker 1o is cut off.

In the above embodiment, if the mode selector switch 27 is switched to the normal mode, normal channel selection operations can be performed, and in this case, the screen of one desired channel can be viewed on the cathode ray tube screen. That is, in this case, if the mode changeover switch 27 is switched to the normal mode, both the electronic switching circuits 17 and 18 are turned off, the signal changeover circuit 21 is connected to the video amplification circuit 5 side, and the audio amplification circuit 9 is in amplification operation. will be carried out. When a desired tuning switch (not shown) is turned on in this state, the switching transistor TR1 of the first tuning circuit 14 corresponding to the switch is turned on.
~One of TR9 is turned on, and the variable resistor VRt~V
The tuning voltage preset by R, is applied to the diode D1.
~DI- is supplied to the tuner 2, and the tuning switch S
W1~SW.

The corresponding channel is in reception status. That is, at this time, the tuner 2, the video intermediate frequency amplification circuit 3, and the video detection circuit 4
, and the video signal received and processed by the video amplification circuit 5 is sent to the cathode ray tube 7 via the signal switching circuit 19 and the video output circuit 6.
The image of the specific channel is displayed on the screen of the cathode ray tube.

At this time, the audio intermediate frequency signal obtained by the video amplification circuit 5 is detected and amplified and then supplied to the speaker 10, from which the audio of the same channel is emitted.

In the above embodiment, an example is described in which a digital storage element such as a RAM is used as the storage device 22, but of course a BBD can also be used.
An analog storage element such as AD may be used in this case.
It becomes possible to omit the converter 23 and the DA converter 25 and to directly store the video signal obtained from the video detection circuit 4 in the storage element.

Further, in the above embodiment, the address counter 22 is stored in the storage device 2.
Although the address counters are used for specifying addresses when writing to and reading from 4, the address counters may be used individually for writing only and for reading only.

According to the television receiver of the present invention, the 9-ary ring p-counter driven by the clock pulse as described above and the 4
A plurality of channels are sequentially selected at a fixed period using an advance/lag counter, and the video information of the plurality of channels obtained in this way is individually written to a plurality of memory elements such as RAM or BBD, and the image is stored in each memory element. Since information is read out sequentially at high speed corresponding to a predetermined position on the screen, images of nine or four channels are displayed simultaneously on the CRT screen by simply switching the mode selector switch when desired. This is very convenient because the user can immediately know the broadcast contents of nine or four channels without having to perform a channel selection operation.

Furthermore, the television receiver of the present invention can be constructed using a smaller number of tuners than the number of images displayed on the cathode ray tube, so that the cost does not increase significantly and the size of the television receiver does not increase.

In particular, according to the television receiver of the present invention, since it is possible to arbitrarily switch between 9 channel images and 4 channel images using the mode changeover switch, almost all receivable channels can be used depending on the viewer's preference. f
: It is extremely convenient because it can be viewed simultaneously on nine split screens, and at other times, four channel images, which are relatively often viewed, can be viewed on a relatively large screen.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the television receiver of the present invention, and FIGS. 2 and 3 are explanatory diagrams of a television screen displayed in the same embodiment. 14... First channel selection circuit, 15...
...Second channel selection circuit, 16...Krosochalus generator, 19 songs old 9-ary ring counter, 20.
・・・・・・Quadary ring counter, 21・・・・・・
・Signal switching circuit, 22...Address counter, 23...AD converter, 24...
...Storage device, 25...DA converter,
26... Music/control signal generation circuit, 27...
...Mode switch agent Patent attorney Aihiko Fukushi

Claims (1)

[Claims] 1. First and second channel selection means for sequentially selecting a plurality of channels at a constant cycle, a storage means for individually writing and storing video information of a plurality of channels obtained by each of the channel selection means, and the storage means. - means for sequentially reading out a plurality of pieces of video information stored in a plurality of pieces of video information corresponding to predetermined positions on the screen, and capable of simultaneously displaying images of several channels on the screen; Each channel selection means uses a 9-ary ring counter and a 4-ary ring counter driven by clock pulses, and a mode changeover switch that selects either ring counter allows 9 or 4 images to be displayed on one screen. A television receiver characterized by being able to display images simultaneously.