JPS588170B2 - Hakeiseikei Cairo - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a waveform shaping circuit used in logic circuits.

The circuit of the present invention will be explained below with reference to the drawings.

FIG. 1 shows a waveform shaping circuit 1 according to the present invention, magnetoresistive elements M and M' as signal sources that generate switch signals input to the waveform shaping circuit, and an output from the waveform shaping circuit. A switching circuit 2 for driving a logic circuit such as a TTL circuit is shown.

The waveform shaping circuit 1 includes a first NPN transistor T1 whose base is connected to an input terminal 11 into which a signal from a signal source is input, and a pair of NPN transistors that operate according to the operation of the first transistor. The configuration includes two transistors T2 and a third transistor T3.

The emitter of the first transistor T1 is grounded, and the collector is connected to the power supply line 1 through the fixed resistor R1.
, that is, connected to the so-called Vcc line.

Further, the collector of the first transistor T1 is connected to the base of the second transistor T2.

Therefore, a voltage divided between the series fixed resistor R1 and the collector-emitter of the first transistor is applied as a bias voltage to the base of the second transistor T2.

The collector of the second transistor T2 is connected to the base of the third transistor T3 via a coupling resistor R2,
On the other hand, the collector of the third transistor T3 has a coupling resistance R
3 to the base of the second transistor T2.

The emitters of the second and third transistors T2 and T3 are each grounded, and the collectors are connected to the power supply line 12 via collector resistors R4 and R5, respectively.

The magnetoresistive elements M and M' are connected in series between the power supply line 12 and the ground, and their intermediate connection points are connected to the input terminal 11 of the waveform shaping circuit 1.

These magnetoresistive elements M and M' are installed, for example, in a pushbutton switch of a keyboard, and configured so that magnetic flux is applied alternately when the pushbutton is operated. In contrast, when the push button is operated, magnetic flux is applied to element M'.

In this way, while the resistance value of element M is high under normal conditions,
' has a low resistance value, and when the push button is operated, the resistance value of element M decreases while the resistance value of element M' increases. Therefore, under normal conditions, a low voltage, that is, a "0" level signal is applied to input terminal 11. During operation, a high voltage, that is, a "1" level signal is applied.

Of course, since it is sufficient to input a switch signal of "0" or "1" level to the waveform shaping circuit 1, one of the magnetoresistive elements M and M' connected in series may be replaced with a fixed resistor. It is also possible to use other non-contact type resistance change elements such as piezoelectric elements and photoelectric elements, and furthermore, a contact type switch may be used as the signal source.

Next, the operation of the waveform shaping circuit 1 will be explained.

When the input terminal 11 is at the "0" level, the first transistor T1 is in an off state, and its collector is at the "1" level.

Since the "1" level of the first transistor turns on the second transistor T2, the collector of the second transistor T2 is at the "0"level;
Since the level is applied to the base of the third transistor T3 via the coupling resistor R2, the third transistor T3 is turned off.

Therefore, in this case, the collector of the third transistor T3 is "1".
” level.

Next, when the input terminal 11 becomes "1" level, the first transistor T1 turns on and its collector becomes "0".
``level'' This turns off the second transistor T2 and its collector goes to level ``1''.
1'' level is connected to the third transistor T via the coupling resistor R2.
3 and the third transistor T3 is turned on.

Therefore, the collector of the third transistor T3 becomes the "0" level.

The switching circuit 2 for driving the logic circuit is an NPN whose base is connected to the collector of the third transistor.
a fourth transistor T4 of type T4;
A diode D1 is connected between the emitter and base of the fourth transistor T4 in a forward direction toward the base, and a terminal X is provided at the emitter of the fourth transistor T4, and a terminal Y is provided at the collector.

Therefore, when the collector of the third transistor T3 of the waveform shaping circuit 1 is at the "1" level, the level of the terminal X is transmitted to the terminal Y because the fourth transistor T4 is in the on state.

For example, if the terminal X is at the "1" level, the terminal Y will be at the "1" level, and if the terminal X is at the "0" level, the terminal Y will be at the "0" level.

On the other hand, when the collector of the third transistor T3 is at the '0' level, the fourth transistor T4 is turned off, so the level of the terminal X is not transmitted to the terminal Y, and the level of the terminal is maintained at the ``0'' level through the

In the above circuit, if the TTL circuit 3 is to be driven as a logic circuit, the connections may be made as shown in FIG. 2 or 3.

In FIGS. 2 and 3, numeral 31 indicates a multi-emitter transistor used as a gate transistor of a TTL circuit, and numeral 32 indicates a phase inversion transistor.

FIG. 2 shows a case where the circuit operates as a positive logic, and the terminal X shown in FIG. 1 is connected to one emitter of the multi-emitter transistor 31.

In this circuit, the third transistor T3 of the waveform shaping circuit 1
As mentioned above, when the collector of the terminal becomes "0" level, the terminal X becomes "0" level.

FIG. 3 shows a case where the circuit operates as a negative logic, and unlike the circuit shown in FIG. 1, the collector of the fourth transistor T4 becomes a terminal X, and one emitter of a multi-emitter transistor 31 is connected to this terminal X.

On the other hand, the emitter of the fourth transistor T4 becomes the terminal Y,
This terminal is grounded via resistor R6.

The operation in this case can be considered by replacing the terminals X and Y in FIG. 1, and when the collector of the transistor T3 goes to the "0" level, the terminal X goes to the "1" level.

In this way, either positive logic or negative logic circuits can be constructed.

Furthermore, it is also possible to drive an LSI circuit in which MOSFET transistors and the like are integrated as shown in FIG. 4 as a logic circuit.

The circuit in FIG. 4 is a diagram showing an example of use in this case, and includes a pair of MOSFET transistors FA and FB and a resistor RA.
, n input circuits F1 composed of diodes DA.
, F2,..., Fn lead terminals X1, X2,
Lead terminal Y1 of m output circuits G1, G2, ......, Gm each consisting of three MOS-FET transistors FC, FD, FE, and grounding resistor RB. , Y2, . . . , Ym, the switching circuits 2, 2, .

FIG. 5 shows an example circuit for increasing the fan-out of the circuit of the present invention, in which the second transistor T2
The switching circuits 2 and 2' are connected to the collectors of both the third transistor T3 and the third transistor T3.

Of course, in this case, the switching circuit 2' constituted by the fifth transistor T3' and the diode D1' operates in the opposite logic to the other switching circuit 2.

Therefore, both positive and negative logic outputs can be obtained simultaneously.

FIG. 6 shows a large number of circuits of the present invention arranged side by side, each first transistor T1, T1, . . . and each second transistor T.
2, T2, . . . , a code conversion matrix circuit 5 is connected between them.

The code conversion matrix circuit 5 constitutes a decimal binary code conversion matrix circuit that converts an input signal input in decimal code into a binary code, as shown in FIG. 7, for example.

In FIG. 7, black circles at intersections indicate connection relationships.

Furthermore, if the signal input to the waveform shaping circuit 1 has a large temperature coefficient, a switch constituted by an element with a large temperature coefficient, such as a magnetoresistive element, may be used as the signal source, for example, as in the above embodiment. When used, as shown in FIG. 8, a PN junction element having a large temperature dependence and a large specific resistance, such as a Schottky diode D4, is connected between the emitter of the first transistor T1 and the ground, and the first transistor T1 is An adjustment resistor R7 may be connected between the emitter and the power supply line 12.

In FIG. 8, the intermediate connection point between the collector of the first transistor T1 and the fixed resistor R1 is connected to the base of the second transistor T2 via a diode D5, but this diode is not necessarily necessary.

The Schottky diode has a large temperature dependence, and its temperature coefficient increases as the current value flowing through the diode decreases as shown in FIG. If the flowing current value is set appropriately, the Schottky diode D4 exhibits appropriate temperature characteristics.

Therefore, the temperature characteristic of the operating point voltage of the first transistor T1 is determined by adding the temperature characteristic of the Schottky diode D4 to the temperature characteristic between the base and emitter of the first transistor T1. In this case, the input signal voltage decreases as the temperature rises, and the temperature characteristic equivalent to this temperature characteristic is determined by the first transistor T.
Temperature compensation can be achieved by setting the operating point voltage to 1.

Incidentally, as mentioned above, the temperature coefficient of the Schottky diode increases as the current decreases, so the Schottky diode D4
Although it is desirable that the resistance value of the adjustment resistor R7 connected in series to the resistor R7 be large, it is difficult to increase the resistance value when integrating the circuit due to space constraints.

Therefore, as shown in FIG. 10, the adjustment resistor R7 is connected between the collector and emitter of the first transistor T1 to connect the base potential of the second transistor T2 to the Schottky diode D.
It is desirable to set the current flowing to 2.

In this way, the resistance value of the adjustment resistor R7 can be made small, making it easy to integrate the circuit, and even when the temperature dependence of the input signal voltage is large, the resistance value of the adjustment resistor R7 can be made small. Therefore, the temperature coefficient of the operating point voltage of the first transistor T1 can be made the same as the temperature characteristic of the input signal voltage.

In the above, the second transistor T2 and the third transistor T3 normally use transistors with the same type of junction, but the first transistor T1 and the second transistor T2 can use transistors with different types of junctions.

For example, when an NPN junction transistor is used as the second transistor T2, a PNP junction transistor can be used as the first transistor T1 as shown in FIG. 11 or 12.

Since the circuit of the present invention is as described above, it has the following effects.

A coupling resistor R3 is connected to the base of the second transistor T2 in parallel with the fixed resistor R1, and is connected to the collector of the third transistor T3 so as to apply a voltage divided from the collector resistor R5. Therefore, the operation compensation of the third transistor when the second transistor T2 is OFF, that is, when the first transistor T1 is ON, is the collector resistance R.
5 and the combined resistor R3, and when the second transistor T2 is inverted from OFF to ON, the amount of current flowing to the base of the second transistor T2 is reduced by the fixed resistor R1 and the combined resistor R3. Since it increases rapidly due to the action, the second transistor T2 operates faster, which has the effect of improving the rise of the switch signal.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of use when the circuit of the present invention is driven by a magnetoresistive element, and FIGS. 2 and 3 are partial circuit diagrams showing examples of use when a TTL circuit is driven by the circuit of the present invention, respectively. The circuit diagram, FIG. 4 is a circuit diagram showing an example of use when driving an LSI circuit using the circuit of the present invention, FIG. 5 is a circuit diagram showing another example of use of the circuit of the present invention, and FIG. A circuit diagram showing an embodiment in which a code conversion matrix circuit is constructed by arranging a large number of inventive circuits in parallel. FIG. 7 is a diagram showing the code conversion matrix circuit described above. FIGS. FIG. 9 is a graph showing the characteristics of the Schottky diode, and FIGS. 11 and 12 are partial circuit diagrams showing other embodiments of the circuit of the present invention. In the figure, T1 indicates the first transistor, T2 the second transistor, and T3 the third transistor.

Claims (1)

[Claims] 1. A first transistor that is opened and closed by a switch signal, a second transistor that performs an inversion operation in response to the opening and closing operation of the first transistor, and a third transistor that performs an inversion operation with respect to the transistor in response to the operation of the second transistor. and the second and third transistors operate in accordance with the opening and closing operations of the first transistor.
and a waveform shaping circuit that takes out an output signal from at least one of the third transistors, a fixed resistor R1 and a coupling resistor R3 are connected to the base of the second transistor in parallel with the power supply, and both resistors are connected to the base of the second transistor in parallel with the power supply. The coupling resistor R3 is connected to the collector of the first transistor so that the second transistor is turned on when the first transistor is off, and the coupling resistor R3 has one end connected to the collector of the third transistor. and the collector resistor, and connect the base of this third transistor to the above-mentioned second transistor.
is connected to the collector of the transistor via a coupling resistor R2, thereby setting the third transistor to be in the off state when the second transistor is in the on state, and between the collector of the third transistor and the base of the second transistor. A waveform shaping circuit characterized in that the coupling resistor R3 in the waveform shaping circuit is configured to compensate for the operation of the third transistor and quickly invert the second transistor to the on state.